Method for fabricating a self-aligned multi-level interconnect

Details Method for fabricating a self-aligned multi-level interconnect Method for fabricating a self-aligned multi-level interconnect

1992-12-30

1995-08-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437193, 437 51, 437 49, H01L 21768

Patent

active

054398487

ABSTRACT:
A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

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