Method for fabricating a self-aligned lightly doped drain semico

Details Method for fabricating a self-aligned lightly doped drain semico Method for fabricating a self-aligned lightly doped drain semico

1988-09-08

1990-06-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 34, 437 41, 437 57, 437192, 437200, 437201, 357 233, 357 42, 357 44, H01L 21265, H01L 2170

Patent

active

049339940

ABSTRACT:
A method for using a self-aligned metallic mask for formation of a shallow source/drain, lightly doped drain metal-oxide-semiconductor device having a self-aligned low-resistivity silicide/polysilicon gate for greater device speed. The invention involves coating a semiconductor wafer in an intermediate stage of processing with a refractory metal layer over a polysilicon layer. The refractory metal layer is patterned and etched to expose corresponding portions of the underlying polysilicon layer, and then the wafer is preamorphized. After appropriate doping of N+ and P+ regions, the semiconductor wafer is subjected to an annealing process, which sinters the metal layer with the underlying polysilicon layer to form a silicide. The silicide provides a low resistivity path for the transistor structures, resulting in greater device speed. Use of the self-aligned metallic mask permits the fabrication of lightly doped drain semiconductor devices having shallow source and drain regions.

REFERENCES:
patent: 4198250 (1980-04-01), Jecmen
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4389257 (1983-06-01), Geipel, Jr. et al.
patent: 4450620 (1984-05-01), Fuls et al.
patent: 4458410 (1984-07-01), Sugaki et al.
patent: 4510670 (1985-04-01), Schwabe et al.
patent: 4530150 (1985-07-01), Shirato et al.
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4577392 (1986-03-01), Peterson
patent: 4587718 (1986-05-01), Haken et al.
patent: 4597163 (1986-07-01), Tsang
patent: 4612258 (1986-09-01), Tsang
patent: 4640844 (1987-02-01), Neppl et al.
Anonymous, "Underlayer for Polycide Process", IBM Technical Disclosure Bulletin, vol. 28, No. 9, Feb. 1986, pp. 3968-3969.
Iyer et al., "New Salicide Spacer Technology", IBM Technical Disclosure Bulletin, vol. 27, No. 3, Aug. 1984, pp. 1801-1802.
Shibata et al., "An Optimally Designated Process for Submicron MOSFETs", IEDM, 1981, pp. 647-650.
Murarka, "Refractory Silicides for Integrated Circuits", J. Vac. Sci. Technol., vol. 17, No. 4, Jul./Aug. 1980, pp. 775-792.
Murarka, Silicides for VLSI Applications, Academic Press, Inc., 1983, pp. 152-156.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 388-391.
Ghandhi, VLSI Fabrication Principles, John Wiley and Sons, Inc., 1983, pp. 351, 358-362.
Ghandhi, VLSI Fabrication Principles, John Wiley and Sons, Inc., 1983, pp. 435-437 and 323-325.
Alperin et al., "Development of the Self-Aligned Titanium Silicide Process for VLSI Applications," IEEE J. of Solid State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 61-69.
Jones et al., "Salicide with Buried Silicide Layer," IBM Technical Disclosure Bulletin, vol. 27, No. 2, Jul. 1984, pp. 1044-1045.
Chow et al., "Refractory MoSi.sub.2 and MoSi.sub.2 /Polysilicon Bulk CMOS Circuits", IEEE Electron Device Letters, vol. EDL-3, No. 2, Feb. 1982, pp. 37-40.

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