Method for fabricating a self-aligned double-gate MOSFET by sele

Details Method for fabricating a self-aligned double-gate MOSFET by sele Method for fabricating a self-aligned double-gate MOSFET by sele

1996-08-01

1997-07-08

Trinh, Michael

Fishing, trapping, and vermin destroying

437 29, 437 41GS, 437 89, 437913, H01L 218234

Patent

active

056460589

ABSTRACT:
A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.

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"Ultrafast Low-Power Operation of P+--n+ Double Gate SOI MOSFETs"; Tanaka et al; Apr. 1994 Symp. on VLSI Technology Digest of Technical Papers IEEE; pp. 11-12.

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