Method for fabricating a poly emitter logic array and apparatus

Details Method for fabricating a poly emitter logic array and apparatus Method for fabricating a poly emitter logic array and apparatus

1989-05-05

1993-09-14

Fourson, George

Fishing, trapping, and vermin destroying

437 49, H01L 2144

Patent

active

052448320

ABSTRACT:
A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a buried perimeter (92) of the metal layer (62). A conductive lead (86) is formed in the Schottky via (68). A poly emitter terminal (46) connects a small sized emitter (50) formed in an epitaxial region (24) to the exterior. Poly emitter (46) presents a large area (76) to the exterior for alignment with a via (66) through a passivating dielectric layer (64), thus alleviating alignment problems.

REFERENCES:
patent: 3717514 (1973-02-01), Burgess
patent: 4063967 (1977-12-01), Graul et al.
patent: 4127931 (1978-12-01), Shiba
patent: 4157269 (1979-06-01), Ning et al.
patent: 4188707 (1980-02-01), Asano et al.
patent: 4214256 (1980-07-01), Dalal et al.
patent: 4424579 (1984-01-01), Roesner
patent: 4425379 (1984-01-01), Vora et al.
patent: 4451326 (1984-05-01), Gwozaz
patent: 4475964 (1984-10-01), Ariizumi et al.
patent: 4504332 (1985-03-01), Shinada
patent: 4516223 (1985-05-01), Erickson
patent: 4569123 (1986-02-01), Ishii et al.
patent: 4579600 (1986-04-01), Shah et al.
patent: 4782030 (1988-11-01), Katsumata et al.
IBM Tech Bulletin, vol. 19, No. 6, Nov. 1976 "Gated Exclusive OR Circuit" F. H. Lohrey and G. J. Robbins.
IEEE Jnl of SS Circuits, vol. SC-20, Oct./1985, "A 150-ps 9000 Gate ECL Masterslice", Walter Brackelmann et al.
Ghandhi; S., VLSI Fabrication Principles: Silicon and Gallium Arsenide, Jan. 1983, pp. 458.

Affiliated with

Also associated with

Rating

Method for fabricating a poly emitter logic array and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a poly emitter logic array and apparatus , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a poly emitter logic array and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2026225