Method for fabricating a poly emitter logic array

Details Method for fabricating a poly emitter logic array Method for fabricating a poly emitter logic array

1985-10-16

1990-02-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 39, 437 46, 437 47, 437 48, 437 50, 437 60, 437175, 437918, 357 51, H01L 2120, H01L 21265, H01L 2956, H01L 2964

Patent

active

048988383

ABSTRACT:
A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a buried perimeter (92) of the metal layer (62). A conductive lead (86) is formed in the Schottky via (68). A poly emitter terminal (46) connects a small sized emitter (50) formed in an epitaxial region (24) to the exterior. Poly emitter (46) presents a large area (76) to the exterior for alignment with a via (66) through a passivating dielectric layer (64), thus alleviating alignment problems.

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