Method for fabricating a plurality of semiconductor chips

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Substrate dicing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

10835732

ABSTRACT:
A semiconductor material (5) is grown in the windows (4) of a patterned mask layer (3) on a substrate (1). The semiconductor material (5) grows together over the mask layer (3) with semiconductor material (5) from adjacent windows to form a largely planar surface (7), which is suitable for the further growth of a component layer sequence (9). Through the choice of a substrate (1) having a smaller thermal expansion coefficient than the semiconductor material (5), particularly strong tensile stresses occur in the semiconductor material (5) or the component layer sequence (9) during cooling, which stresses lead to cracking. Since the semiconductor material (5) that has grown together forms a so-called coalescence region (6), having a high density of imperfections in the crystal lattice, these thermally governed cracks (13) are more likely to occur in this region. If the semiconductor bodies are singulated along these regions, these regions high in defects can be removed during the singulation, and a semiconductor body of high crystal quality can be mass produced.

REFERENCES:
patent: 5828088 (1998-10-01), Mauk
patent: 6156584 (2000-12-01), Itoh et al.
patent: 6252261 (2001-06-01), Usui et al.
patent: 6325850 (2001-12-01), Beaumont et al.
patent: 6377596 (2002-04-01), Tanaka et al.
patent: 6482666 (2002-11-01), Kobayashi et al.
patent: 6670204 (2003-12-01), Tanabe et al.
patent: 6815241 (2004-11-01), Wang
patent: 6818463 (2004-11-01), Biwa et al.
patent: 2001/0007242 (2001-07-01), Davis et al.
patent: 2002/0038870 (2002-04-01), Kunisato et al.
patent: 2003/0001238 (2003-01-01), Ban
patent: 2004/0192016 (2004-09-01), Harle et al.
patent: 102 18 498 (2003-11-01), None
patent: 0942459 (1999-09-01), None
patent: 10320160 (2003-05-01), None
patent: 2000-174334 (2000-06-01), None
patent: 2000174334 (2000-06-01), None
patent: 9963582 (1999-12-01), None
JPO Machine translation of 2000-174334.
Y. H. Song et al., “Lateral Epitaxial Overgrowth of GaN and its Crystallographic Tilt Depending on the Growth Condition”, Phys. Stat. Sol. (a) 180, 247 (2000).
B. Beaumont et al., “Expitaxial Lateral Overgrowth of GaN”, Phys. Stat. Sol. (b) 227 (2001), No. 1, pp. 1-43.
X. Li et al., “GaN Epitaxial Lateral Overgrowth and Optical Characterization”, Applied Physics Letters (1998), vol. 73, No. 9, pp. 1179-1181.
L.D. Zhu et al., “Epitaxial Growth and Structural Characterization of Single Crystalline ZnGeN2”, MRS Internet J. Nitride Semicond. Res. 4S1, G3.8 (1999).
S. Nakamura et al., “The Blue Laser Diode” pp. 34-77, Springer-Verlag 1997.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating a plurality of semiconductor chips does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a plurality of semiconductor chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a plurality of semiconductor chips will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3850630

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.