Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1998-09-28
2001-06-05
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S514000
Reexamination Certificate
active
06242314
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to fabrication of polysilicon resistors for semiconductor devices and particularly to the fabrication of a resistor with both p-type and N-type doping and more particularly to an On-chip temperature controller having polysilicon load resistors that have both p-type and N-type doping by a ion co-implant process.
2) Description of the Prior Art
As the device dimensions decrease and the packing density increases, the power dispassion becomes a major consideration in circuit operation. In the future, the on-chip temperature sensor to detect and control temperature variation will become more important.
For the traditional power transistor, the large current flow and high operation voltage will also increase temperature rapidly, which can damage the power device and decrease the lifetime of the circuit. It important that the resistor have a low temperature coefficient (i.e., low change in resistivity with temperature change).
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,298,401 (Nuez) that shows a breakdown voltage resistor obtained through a double ion-implantation (Both same conductivity resistor) into a semiconductor substrate.
U.S. Pat. No. 4,762,801 (Kapoor) shows an amorphous poly resistor and I/I an impurity to give the resistor the proper Temp coefficients.
U.S. Pat. No. 5,037,766 (Wang) shows a poly resistor treated with an Oxygen treatment.
U.S. Pat. No. 5,489,547 (Erdeljac) shows a method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient.
However, the temperature coefficient's of poly load resistors can be further improved.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a resistor in an on-chip temperature sensor that has an easily controllable cut off temperature.
It is an object of the present invention to provide a method for fabricating a resistor in an on-chip temperature sensor that has an easily controllable resistivity that allows exact temperature cut off s point to be defined in a temperature controller.
It is an object of the present invention to provide a method for fabricating a resistor in a on-chip temperature sensor that has a easily controllable cut off temperature which is low cost and simple to manufacture.
It is an object of the present invention to provide a method for fabricating a resistor with both P and N type implanted impurities in a on-chip temperature sensor that has a easily controllable cut off temperature.
To accomplish the above objectives, the present invention provides a method of manufacturing an on-chip temperature controller including the steps of: forming a first insulation layer
20
over a semiconductor structure
10
. Next, we form a polysilicon layer
30
on the first insulation layer
20
. The polysilicon layer
30
is patterning to form a first poly-load resistor and a second poly-load resistor. The first and the second poly-load resistors are connected to a temperature sensor circuit
12
. Both p-type and n-type impurity ions are implanted into the polysilicon layer
30
.
An insulating (e.g., interlevel dielectric (ILD)) dielectric layer
40
is formed over the polysilicon layer
30
and the first insulating layer
20
.
The polysilicon layer is rapid thermal anneal the polysilicon layer at a Temperature in a range of between about 900 and 1100° C. for a time in a range of between about 10 and 20 seconds. The polysilicon layer
30
preferably has a n-type impurity ion concentration in a range of between about 1E18 and 1E19 atoms/cm
3
and a p-type impurity ion concentration in a range of between about 5E17 and 5E18 atoms/cm
3
; and the polysilicon layer having sheet resistance in a range of between about 1 Meg ohm and 1 Gig-ohm and TC temperature coefficient in a range of between about −20 and 200.
The contact openings
44
if formed through the ILD dielectric layer
40
exposing portions of the polysilicon layer
30
.
Contacts
50
to the polysilicon layer
30
thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors, the first and second poly-load resistors have different implant dose to get the desired cut off temperatures.
Benefits
The present invention provides the following benefits:
1) The invention's N and P impurity co-implant, the poly-load resistor resistance can be controlled to achieve the desired cut off temperature.
2) The invention's poly-load resistor only occupies a small area and will allow dense packing.
The co-implant affects the temperature coefficient of the resistors as shown in the
FIGS. 5 & 6
. The different doses have different cross over points. The designer can use these as parameters. The co-implanted poly-load resistors have low temperature coefficient.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 4298401 (1981-11-01), Nuez et al.
patent: 4602421 (1986-07-01), Lee et al.
patent: 4679170 (1987-07-01), Bourassa et al.
patent: 4707909 (1987-11-01), Blanchard
patent: 4762801 (1988-08-01), Kapoor
patent: 5037766 (1991-08-01), Wang
patent: 5489547 (1996-02-01), Erdeljac et al.
patent: 5622884 (1997-04-01), Liu
Lee et al, On the semi-insulating polycrystalline silicon resistor, Solid State Electronics, vol. 27, No. 11, pp. 995-1001, 1984.
Chen Shui-Hung
Jung Lin Chrong
Shih Jiaw-Ren
Ackerman Stephen B.
Hoang Quoc
Nelms David
Saile George O.
Stoffel William J.
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