Method for fabricating a MOSFET device, with local channel dopin

Details Method for fabricating a MOSFET device, with local channel dopin Method for fabricating a MOSFET device, with local channel dopin

1996-08-01

1997-11-18

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437192, 437984, H01L 21266

Patent

active

056887060

ABSTRACT:
A process has been developed in which a deep submicron MOSFET device has been fabricated, featuring a local, narrow threshold voltage adjust region, in a semiconductor substrate, with the local, narrow threshold voltage adjust region, self aligned to an overlying, narrow tungsten-polysilicon gate structure. The process consists of forming a narrow hole opening in an insulator layer, where the insulator layer overlies a polysilicon layer and a gate insulator layer. An ion implantation procedure, through the polysilicon layer, and gate insulator layer, is used to place a narrow threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. Selective deposition of tungsten results in the creation of a tungsten gate structure, in the narrow hole opening, on the top surface of the polysilicon layer. Patterning of the polysilicon layer, using the overlying tungsten gate structure as a mask, results in an polysilicon gate structure, underlying the tungsten gate structure, in the narrow hole opening. The composite narrow tungsten-polysilicon gate structure is self aligned to the underlying, local, narrow threshold voltage adjust region.

REFERENCES:
patent: 5219777 (1993-06-01), Kang
patent: 5413949 (1995-05-01), Hong
patent: 5464782 (1995-11-01), Koh
patent: 5489543 (1996-02-01), Hong
patent: 5504038 (1996-04-01), Chien et al.

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