Method for fabricating a MOS transistor with two-layer inverse-T

Details Method for fabricating a MOS transistor with two-layer inverse-T Method for fabricating a MOS transistor with two-layer inverse-T

1994-11-22

1997-02-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437913, 437192, H01L 218234

Patent

active

055997252

ABSTRACT:
The present invention is directed to a unique method for fabricating a silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

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