Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-01-19
2003-05-06
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S724000, C438S742000, C438S754000, C438S756000
Reexamination Certificate
active
06559059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a MOS transistor of an embedded memory, and more particularly, to a manufacturing method of a MOS transistor of an embedded memory to simultaneously form a periphery circuit region and a memory array area.
2. Description of the Prior Art
With increasing integration, the present trend of manufacturing semiconductor integrated circuits is to integrate memory cell arrays and high-speed logic circuit elements onto a single chip. An embedded memory composed of memory arrays and logic circuits significantly reduces the circuit area and increases the signal processing speed. The high-speed logic circuit element is also called a periphery circuit region.
Because the MOS transistors formed in the periphery circuit region requires low resistance and high speed, the present semiconductor process primarily uses a self-alignment silicide (salicide) process to form a silicide layer on each gate, source and drain of the MOS transistors formed on the periphery circuit region for reducing the surface resistance of each gate, source and drain of the MOS transistors. However, the self-aligned-contact (SAC) process developed for solving the electrical connection problem of memory cells in the memory array area involves forming a silicon nitride layer, as a cap layer, and a spacer on the top and side surfaces of a gate of a pass transistor formed in the memory array area as an isolation mask in the subsequent SAC process. Therefore, in the prior art method, the two processes conflict and are not performed simultaneously, resulting in increased time and cost.
Please refer to
FIG. 1
to
FIG. 9
FIG. 1
to
FIG. 9
are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer
10
. As shown in
FIG. 1
, the surface of the silicon substrate
16
is divided into a memory array area
12
and a periphery circuit region
14
, and each region is separated by several shallow trench isolation structures
11
. The prior art method involves forming a dielectric layer
18
, a polysilicon layer
20
and an etching barrier layer
22
, respectively, on the surface of the semiconductor wafer
10
. Then, as shown in
FIG. 2
, a mask layer
24
is formed over the etching barrier layer
22
in the periphery region
14
. The etching barrier layer
22
and the polysilicon layer
20
in the memory array area
12
are removed using an isotropic wet etching operation.
As shown in
FIG. 3
, the mask layer
24
above the etching barrier layer
22
is removed, and then the dielectric layer
18
in the memory array region
12
is stripped away to expose the substrate surface
16
. As shown in
FIG. 4
, a dielectric layer
26
is formed over the exposed substrate
16
, and serves as a gate oxide layer in the memory array area
12
. Thereafter, a polysilicon layer
28
, a tungsten silicide layer
30
and a silicon nitride layer
32
are formed, respectively, over the surface of the semiconductor wafer
10
.
In the next step, as shown in
FIG. 5
, a photoresist layer
34
is deposited over the silicon nitride layer
32
and a lithographic process is performed to define gate patterns in the memory array area
12
and periphery circuit region
14
. Next, using the photoresist layer
34
as a mask, the silicon nitride layer
32
, the tungsten silicide layer
30
and the polysilicon layer
28
are etched, thereby exposing portions of the dielectric layer
26
in the memory array area
12
and portions of the etching barrier layer
22
in the periphery circuit region
14
. As shown in
FIG. 6
, the photoresist layer
34
is removed. Thereafter, another photoresist layer
36
is deposited over the memory array area
12
for protecting the gate
33
structure, which includes the dielectric layer
26
, the polysilicon layer
28
, the tungsten silicide layer
30
and the silicon nitride layer
32
.
As shown in
FIG. 7
, the photoresist layer
36
and the silicon nitride layer
32
of the periphery circuit region
14
are used as hard masks to remove the etching barrier layer
22
and the polysilicon layer
20
not covered by the silicon nitride layer
32
in the periphery circuit region
14
. A gate
35
structure of the periphery circuit region
14
is formed, and the silicon nitride layer
32
, the tungsten silicide layer
30
, the polysilicon layer
28
and the photoresist layer
36
are then removed.
As shown in
FIG. 8
, an ion implantation process is performed to form lightly doped drain (LDD)
38
structures of the MOS transistors. Next, a silicon nitride layer
43
is deposited over the semiconductor wafer
10
, followed by an anisotropic etching process to form spacers
44
on the walls of the gate
35
structures in the periphery circuit region
14
. The remaining etching barrier layer
22
is removed after the formation of the spacers
44
. A source
40
and a drain
42
of the MOS transistors are then formed in the periphery circuit region
14
. Finally, as shown in
FIG. 9
, a self-aligned silicide operation is carried out to form a salicide layer
46
above each source
40
, drain
42
and gate
35
structure in the periphery circuit region
14
.
However, in
FIG. 5
of the prior art method, the etching process is simultaneously performed in the memory array area
12
and in the periphery circuit region
14
to simultaneously form patterns of the gates. The density of the gates in the memory array area
12
is normally greater than that of the periphery circuit region
14
, resulting in the etching process causing both a proximity effect and a loading effect. As well, in
FIG. 7
, an extra step is needed to remove the silicon nitride layer
32
in the periphery circuit region
14
, when the silicon nitride layer
32
is not necessary for the gates
35
in the periphery circuit region
14
.
SUMMARY OF THE INVENTION
It is a primary objective of the present invention to provide a method of manufacturing a MOS transistor of an embedded memory to solve the above-mentioned problems.
The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to sequentially deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer, followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer, and the passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed. Finally, the undoped polysilicon layer is etched to form a plurality of gates in the periphery circuit region, followed by the respective formation of spacers, sources and drains of each MOS transistor in the periphery circuit region.
There are two advantages of the present invention, the first of which is the simultaneous formation of the silicon nitride layer necessary for the gates in the memory array area and removal of the silicon nitride layer not necessary for the gates in the periphery circuit region. In the prior art method, after etching the gates in both the memory array area and in the periphery circuit region, an extra step is needed to remove the silicon nitride layer not necessary for the gates in the periphery circuit region to increase time cost. The second advantage is that the present invention performs the etching process to form separately the gates in the memory array area and those in the periphery circuit region to reduce both the proximity effect and the loading effect since the density of gate patterns of the DRAM is higher in the memory array than in the periphery circuit regio
Chien Sun-Chieh
Kuo Chien-Li
Hsu Winston
Powell William A.
United Microelectronics Corp.
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