Method for fabricating a MOS transistor

Details Method for fabricating a MOS transistor Method for fabricating a MOS transistor

1995-07-19

1998-06-30

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 47, 437186, H01L 21335, H01L 218242

Patent

active

057733104

ABSTRACT:
A transistor fabricated by a characteristic method which comprises forming a source/drain region prior to the formation of a gate electrode and then, forming source/drain pads which are in contact with the source/drain and insulated from the gate electrode, comprising a MOSFET structure in which two identical conductors are a predetermined distance away from each other on a semiconductor substrate beneath each of which a source/drain diffusion region is formed in electrical connection with it and between which a gate oxide film is formed on the semiconductor substrate, and a gate electrode extends over the two separated connectors while being insulated therefrom. It secures enough mask alignment allowance and is widely applied not only to transistors but also to DRAMs or SRAMs.

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patent: 5240872 (1993-08-01), Motonami et al.
patent: 5416034 (1995-05-01), Bryant
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Proceeds Technology, Calif., Lattice Press, 1986, p. 527.

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