Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2002-07-26
2004-08-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S244000, C438S660000, C438S702000, C438S703000, C438S795000
Reexamination Certificate
active
06774005
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating a metal carbide layer and a method for fabricating a trench capacitor for use in a semiconductor memory cell.
In dynamic random access memory cell configurations, it is virtually exclusively that single-transistor memory cells are used. A single-transistor memory cell contains a read transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge that represents a logic 0 or a logic 1. Actuating the read transistor via a word line allows the information to be read via a bit line. The storage capacitor must have a minimum capacitance for reliably storing the charge and, at the same time, to make it possible to differentiate the information item that has been read. The lower limit for the capacitance of the storage capacitor is currently considered to be 25 fF.
Since the storage density increases from memory generation to memory generation, the surface area required by the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor has to be retained.
Up to the 1 Mbit generation, both the read transistor and the storage capacitor were produced as planar components. Beyond the 4 Mbit memory generation, the area taken up by the memory cell was reduced further by using a three-dimensional configuration of the read transistor and storage capacitor. One possibility is for the capacitor to be produced in a trench (see the reference by K. Yamada et al., Proc. Intern. Electronic Devices and Materials IEDM 85, pp. 702 ff.). In this case, a diffusion region which adjoins the wall of the trench and a doped polysilicon filling disposed in the trench act as electrodes for the storage capacitor. Therefore, the electrodes of the storage capacitor are disposed along the surface of the trench. In this way, the effective surface area of the storage capacitor, on which the capacitance is dependent, is increased with respect to the space taken up by the storage capacitor on the surface of the substrate, which corresponds to the cross section of the trench. Although there are limits on the extent to which the depth of the trench can be increased, for technological reasons, the packing density can be further increased by reducing the cross section of the trench.
However, one difficulty of the decreasing trench cross section is the increasing electrical resistance of the trench filling and the associated increase in the read-out time of the DRAM memory cell. Therefore, to ensure a high read-out speed as the trench cross section is further reduced in size, it is necessary to select materials with a lower resistivity for the electrodes of the trench capacitor. In current trench capacitors, the trench filling consists of doped polycrystalline silicon, so that as miniaturization continues a high series resistance of the trench filling results.
There have already been various proposals for depositing a metal or a layer sequence which contains a metal-containing layer onto the storage dielectric in the trench. A general problem in this context is the high aspect ratio of the capacitor trench into which a layer sequence has to be deposited if possible in such a manner that it forms a good and permanent mechanical and electrical contact with the storage dielectric below it and that no voids are formed within the capacitor electrode. A further problem is that many metals do not have a particularly high ability to withstand heat.
Published, European Patent Application EP 0 981 158 A2 describes the fabrication of a DRAM memory cell which has a trench capacitor and a select transistor which is connected thereto via a buried strap. The trench capacitor has a lower capacitor electrode, which adjoins a wall of the trench, a capacitor dielectric and an upper capacitor electrode. The trench capacitor is fabricated by forming the upper capacitor electrode in the lower trench region, then depositing an insulating collar in the upper trench region, and then completing the upper capacitor electrode. With regard to the trench filling which forms the upper capacitor electrode, it is specifically stated that this filling may be formed by a metal both in the lower region of the trench and in the upper region of the insulating collar. In any event, however, the trench filling in the region of the insulating collar is formed in one step and therefore from the same material as the buried strap. Therefore, if a metal is formed into the insulating collar, the buried strap also has to be formed from metal. However, in this context it is possible that the select transistor may be adversely affected by the contact that is made with a highly conductive material at the drain region. Moreover, no details are given as to the nature of the metal that is to be used.
U.S. Pat. No. 5,905,279 discloses a memory cell having a storage capacitor disposed in a trench and a select transistor. The storage capacitor has a lower capacitor electrode, which adjoins a wall of the trench, a capacitor dielectric and an upper capacitor electrode. The upper capacitor electrode contains a layer stack formed of polysilicon, a metal-containing, electrically conductive layer, in particular made from WSi, TiSi, W, Ti or TiN, and polysilicon. The trench capacitor is fabricated by first forming the upper capacitor electrode in the lower trench region. Then, an insulating collar is deposited in the upper trench region, and next the upper capacitor electrode is completed. Alternatively, the method is carried out on a silicon-on-insulator (SOI) substrate which does not have an insulating collar, in which case the upper capacitor electrode, which contains a lower polysilicon layer and a tungsten silicide filling, is fabricated in a single-step deposition method, in which the individual layers are deposited entirely in the trench. Although the metals described in this document, such as tungsten, titanium or silicides thereof, are highly temperature stable, the reduction in the series resistance of the upper capacitor electrode which can be achieved in theory with this method is still unsatisfactory.
International Patent Disclosure WO 01/29280 discloses a method for depositing thin layers of metal carbide by an alternating deposition of a transition metal layer and a carbon layer with layer thicknesses at the atomic level (atomic layer deposition (ALD)) on a substrate. Rearrangement processes on the heated substrate result in the formation of a metal carbide layer in situ.
U.S. Pat. No. 5,680,292 likewise describes, inter alia, a method for forming tungsten or molybdenum carbide layers. First, a corresponding metal oxide layer is deposited, and then the layer is subjected to a carbon treatment at elevated temperature in an oxygen-reducing environment.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a metal carbide layer and a method for fabricating a trench capacitor containing a metal carbide which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which makes it possible to form the trench capacitor with a reduced series resistance and a high thermal stability. A second object of the present invention is to provide a method for fabricating a metal carbide layer that is able to simplify the shaping or patterning of the metal carbide layer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a trench capacitor for use in a semiconductor memory cell. The method includes the steps of providing a substrate, forming a trench in the substrate, forming a lower capacitor electrode adjoining a wall of the trench in a lower trench region, and providing a storage dielectric. In the trench, the storage dielectric adjoins the lower capacitor electrode. An upper capacitor electrode is provided and is formed as a trench filling and adjoins the storage dielectric. The uppe
Gutsche Martin
Moll Peter
Sänger Annette
Seidl Harald
Sell Bernhard
Fourson George
García Joanne Adelle
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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