Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2005-02-15
2005-02-15
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S777000, C438S107000
Reexamination Certificate
active
06856014
ABSTRACT:
A method of individually packaging a multiplicity of devices, such as a spatial light modulator, before the multiplicity of devices formed on a substrate wafer are separated. The method and structure comprises individually sealing each device while the device is still part of sealed by the combination interposer wafer and a cover or window wafer. After each device is sealed by the combination interposer wafer and cover wafer, the combination cover wafer is sawed through down to the substrate wafer. The sealed devices may then be fully separated by scoring and breaking the substrate wafer.
REFERENCES:
patent: 5798557 (1998-08-01), Salatino et al.
patent: 5915168 (1999-06-01), Salatino et al.
patent: 6586831 (2003-07-01), Gooch et al.
patent: 6639313 (2003-10-01), Martin et al.
patent: 6686657 (2004-02-01), Kline
patent: 6762868 (2004-07-01), Liu et al.
patent: 20030128044 (2003-07-01), Pierce
Ehmke John C.
Harris John Paul
Lopes Vincent C.
Brady III Wade James
Brill Charles A.
Clark S. V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Method for fabricating a lid for a wafer level packaged... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a lid for a wafer level packaged..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a lid for a wafer level packaged... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3497088