Method for fabricating a high coupling ratio flash memory with a

Details Method for fabricating a high coupling ratio flash memory with a Method for fabricating a high coupling ratio flash memory with a

1995-09-01

1996-05-28

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437979, H01L 218247

Patent

active

055211097

ABSTRACT:
A method for fabricating a high coupling ratio flash memory includes the steps of forming a field oxide region and a gate oxide layer on the substrate; forming a silicon nitride layer on the gate oxide layer and defining a channel region under the gate oxide layer; forming two N.sup.- shallow doping regions beside the channel region; forming a tunnel layer on the surface of each N.sup.- shallow doping region; forming two insulator side wall layers respectively attached to two vertical sides of the silicon nitride layer and the gate oxide layer, with a portion of the tunnel oxide layer being covered by the two silicon nitride layers; removing a portion of the tunnel layer and leaving two very short tunnel oxide layers respectively covered by the two silicon nitride layers; forming a thick oxide layer on N.sup.+ source/drain regions substantially between the field oxide region and the insulator side wall layers, removing the silicon nitride layer and the insulator side wall layer; forming a first polysilicon layer on a portion of the thick oxide layer and the gate oxide layer; forming a dielectric layer and a second polysilicon layer.

REFERENCES:
patent: 5153144 (1992-10-01), Komori et al.
patent: 5225362 (1993-07-01), Bergemont
patent: 5352618 (1994-10-01), Larsen et al.
patent: 5453393 (1995-09-01), Bergemont

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