Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2002-05-31
2004-04-20
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S581000, C438S649000, C438S754000, C438S755000
Reexamination Certificate
active
06723657
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating a gate stack in very large scale integrated semiconductor memories.
The integration of semiconductor circuits with a very large scale packing density requires gate stacks which have a very low sheet resistance (less than 5 to 10 ohms/unit area), in order to reduce time delays caused by inevitable RC paths. At the same time, the DRAM technology for the fabrication of compact bit cells requires the formation of self-aligning contact sections.
Heretofore, it has been attempted to solve those problems by using gate stacks formed of tungsten silicide. Unfortunately, gate stacks of that type have a high sheet resistance (for example approximately 25 ohms/unit area). If one attempts to reduce the sheet resistance by making the silicide layer thicker, the complexity of the processes is increased, since each stack etching process lasts longer and the contact etching process has to reach a deeper level. The use of lower-resistance silicides (CoSi
2
or TiSi
2
) involves the problem of a stack of polysilicon and Co or Ti silicide not being able to be etched and having a low thermal stability during subsequent stack processes. Other types of gate stack materials, such as for example WN/W, are of limited use due to their insufficient stability under oxidizing process conditions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a gate stack, in particular in very large scale integrated semiconductor memories, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type in such a way that the gate stack has a low resistance, can be fabricated by using conventional materials and is compatible with a self-aligning contact section.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a gate stack above a substrate section of a semiconductor memory covered by a gate oxide layer, in very large scale integrated semiconductor memories. The method comprises the following steps:
a) applying a polysilicon layer above the gate oxide layer;
b) applying a silicon nitride layer above the polysilicon layer as a mask layer for a subsequent damascene process;
c) selectively etching an opening, with a side wall and a base, into the silicon nitride layer, down to the polysilicon layer, in the relevant substrate section;
d) covering the silicon nitride layer, including the side wall and the base of the opening, with a Ti or Co layer;
e) converting the Ti or Co at the base of the opening into a silicide section through a conditioning process;
f) removing unsilicided Ti or Co;
g) forming a covering layer entirely over the substrate section, covering the silicon nitride layer and filling the opening above the silicide section;
h) removing the covering layer down to the silicon nitride layer, while retaining the covering layer in the opening;
i) selectively etching the silicon nitride layer down to the polysilicon layer, leaving a gate stack formed of TiSi
2
or CoSi
2
and a section of the covering layer remaining above the TiSi
2
or CoSi
2
, in the opening;
j) selectively etching the polysilicon layer down to the gate oxide, with the gate stack functioning as a hard mask; and
k) applying a spacer wall around a periphery of the gate stack.
The fact that the method according to the invention, in a significant aspect, uses a damascene process (either nitride, as illustrated, or oxide) to form a thick, self-aligning silicide gate layer (either TiSi
2
or CoSi
2
), on which a covering layer formed either of oxide or nitride can then be deposited, means that the invention is able to form self-aligning contacts. The gate stack achieves a sheet resistance of <1 ohm/unit area and can be fabricated by using standard materials. This method can be used particularly advantageously for the fabrication of very large scale integrated semiconductor memories or for embedded memories.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a gate stack in very large scale integrated semiconductor memories, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5851890 (1998-12-01), Tsai et al.
patent: 6074922 (2000-06-01), Wang et al.
patent: 6184117 (2001-02-01), Lu
patent: 6423634 (2002-07-01), Wieczorek et al.
patent: 6602781 (2003-08-01), Xiang et al.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Vinh Lan
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