Method for fabricating a ferroelectric memory configuration

Details Method for fabricating a ferroelectric memory configuration Method for fabricating a ferroelectric memory configuration

2001-12-26

2002-12-31

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000, C438S241000

Reexamination Certificate

active

06500677

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating a ferroelectric memory configuration. The present invention relates in particular to a method for fabricating a ferroelectric memory configuration having a memory cell array including a multiplicity of memory cells. Each of the memory cells has at least one select transistor and a storage capacitor and can be activated by word and bit lines.
Ferroelectric memory configurations, as are described, for example, in European Patent Application No. EP 0 516 031 A1, corresponding to U.S. Pat. Nos. 5,495,117 and 5,580,814, or in Yamaziki et al., IEDM, 1997, pp 613-616, compared to conventional memory configurations, such as for example DRAMs and SRAMs, have the advantage that the stored information is not lost, but rather remains stored, even if the voltage or current supply is interrupted. This nonvolatile nature of ferroelectric memory configurations is based on the fact that, when using ferroelectric materials, the polarization that is applied by an external electric field is substantially retained even after the external electric field has been disconnected.
However, in integrated circuits, minor voltage differences between the electrodes of the ferroelectric storage capacitors that are unintentionally occurring are impossible to prevent. These minor voltage differences often occur as a result of parasitic components. Depending on the polarization of the ferroelectric material of the storage capacitor and depending on the polarity of the voltage differences, the voltage differences reinforce or attenuate the polarization of the ferroelectric material. The voltage differences between the electrodes also can be regarded as spurious pulses. Depending on the number and/or amplitude of the spurious pulses, the stored information is attenuated to a greater or lesser extent. In extreme circumstances, the result may even be an incorrect assessment when the memory configuration is read, which in practice corresponds to the data being lost.
This is to be explained in more detail with reference to
FIG. 10
, in which the hysteresis curve of a ferroelectric storage capacitor is plotted. This hysteresis curve shows that when a voltage V=0 is present, there are two polarization states P, with the result that information can be stored. In the example shown in
FIG. 10
, a polarization P is written to the material of the storage capacitor as a result of a positive voltage V being applied. The voltage V is then returned to the value V=0, and a polarization P which differs from 0 (c.f. reference 17) is retained in the ferroelectric storage capacitor.
If, for example as a result of a spurious pulse
19
, the polarization migrates from the point
17
to a point
18
and the voltage
0
is present again after the spurious pulse has decayed, the polarization does not return to the point
17
, but rather migrates to a point
20
that lies below the point
17
. In this way, a plurality of spurious pulses may ultimately lead to the information being lost.
The introduction of spurious pulses when a memory configuration is operating also depends on the operating concept used for the memory configuration. In particular, when using the so-called VDD/2 concept, the capacitive introduction of voltage fluctuations at a common electrode of all the ferroelectric storage capacitors, for example when the memory configuration is switched on and off, and leakage currents of blocked PN junctions lead to spurious pulses. When using the pulsed concept, in particular capacitive overcoupling of a pulsed electrode bar on unselected memory cells leads to spurious pulses. Furthermore, in the VDD/2 and pulsed concepts, charge injection and capacitive introduction of the select transistor or transfer gate cause spurious pulses. Finally, when using the NAND concept, the voltage drop at the transistors as a result of the flow of current that occurs when reading and writing a memory cell causes spurious pulses.
Two approaches attempt to solve the leakage current problem encountered in the VDD/2 concept: both are based on the charge that flows through the blocked PN junction being topped up either continuously or cyclically by the select transistor of the memory cell. However, continuously switching on the select transistors is only possible when the memory configuration is not being accessed. This is because if the memory configuration is being accessed, only one word line of the memory cell array may be active, while all the other word lines must be switched off. Therefore, after the memory has been accessed, it is then necessary for all the word lines to be switched on again, which leads to a consider rise in power consumption on account of the high capacitive load. Cyclically switching on the select transistors also has the drawback that, on account of the leakage current between the cycles, spurious pulses occur at the storage capacitors, and it is at most possible to limit the amplitude of these pulses.
An additional difficulty is that the leakage current of a blocked PN junction is not only subject to considerable fluctuations but also rises substantially as the temperature rises.
In the pulsed concept, to save on chip area and to shrink the memory configuration, generally twice as many storage capacitors are connected to a common electrode bar as are addressed during a read or write access operation. To avoid this difficulty, therefore, the base surface area of a memory cell would have to be increased considerably, but this is undesirable for cost reasons.
In the case of a NAND-like configuration of the memory cells, which can also be used in combination with the VDD/2 concept, the leakage current problem of blocked PN junctions is substantially solved. However, the finite resistance of the transistors during reading or writing of the memory cells causes spurious pulses to occur at the adjacent cells.
To avoid the information losses caused by spurious pulses, it has been proposed in German Published, Non-Prosecuted Patent Application DE 198 32 994 A1, corresponding to U.S. Patent Application Publication US 2001/0012213A1, which is commonly-owned and not a prior publication, for an additional short-circuit transistor to be provided for each storage capacitor, which transistor is able to suitably short-circuit the electrodes of the storage capacitor. By way of example, activation of the short-circuit transistor after each read or write operation allows both electrodes of the storage capacitor to be brought to the same potential via the short-circuit transistor. In this way, disadvantageous influences of spurious pulses on the polarization of the ferroelectric material, in particular the build-up of a potential difference between the electrodes of the storage capacitor, can be considerably reduced or avoided.
However, with a view to the fabrication process, it is not easy to integrate an additional transistor in a ferroelectric memory cell and, in particular, to connect both electrodes of the storage capacitor to this additional transistor. Therefore, the object of the present invention is to provide a simple and inexpensive method for fabricating ferroelectric memory cells with an additional short-circuit transistor.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a ferroelectric memory configuration that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a ferroelectric memory configuration. The first step of the method is providing a substrate having a multiplicity of memory cells. Each of the memory cells have a select transistor, a short-circuit transistor, and a ferroelectric capacitor having an electrode. The select transistor and the short-circuit transistor is electrically connected to the electrode of the ferroelectric capacitor. The next step is applying an electr

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