Method for fabricating a DRAM cell structure on an SOI wafer inc

Details Method for fabricating a DRAM cell structure on an SOI wafer inc Method for fabricating a DRAM cell structure on an SOI wafer inc

1997-11-20

1999-11-02

Bowers, Charles

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

438244, 438386, 438393, H01L 2120

Patent

active

059769459

ABSTRACT:
A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.

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Nishihara et al, "A Buried Capacitor Cell with Bonded SIO for 256-Mbit and 1-Gbit DRAMs" Solid State Technology, Jun. '94. pp. 89-94.

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