Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
1999-08-23
2001-01-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
Reexamination Certificate
active
06171923
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory, (DRAM), cell, on a semiconductor substrate.
(2) Description of Prior Art
The ability to continually increase the signal of DRAM devices, via capacitance increases, using a stacked capacitor configuration, is limited by the dimension of the underlying transfer gate transistor. The reduced dimensions of the underlying transfer gate transistor limit the amount of capacitor area available for an overlying stacked capacitor structure, thus motivating semiconductor device designers, and process engineers, to migrate to DRAM cells, incorporating trench capacitors. The ability to create the DRAM capacitor in a trench in the semiconductor substrate, has allowed DRAM devices densities of 64 Mbit and greater to be achieved.
This invention will offer a fabrication sequence used for the creation of high density DRAM designs, using a two dimensional trench capacitor structure. The use of a silicon on insulator, (SOI), layer, incorporated in this invention, allows an undercutting of the trench to occur, in the region in which the trench resides in the insulator layer, underlying the SOI layer, resulting in an increase in capacitor surface area, for a specific trench depth. In addition the storage node capacitor layer, residing on the sides of the trench, shorts the SOI layer to the semiconductor substrate, thus eliminating a floating body effect that can occur with DRAM structures, fabricated in on a SOI layer. Prior art such as Tang, U.S. Pat. No. 5,585,285, shows a trench through an SOI layer, but does not show the intentional undercut used in this invention, offering additional capacitor surface area. Ohtsuki, et al, in U.S. Pat. No. 5,629,226, describe a DRAM device, using a trench capacitor, with the bottom of the trench widened using diffusion procedures. However none of these prior arts describe a DRAM device, using the combination of a lateral undercut in a trench, and the elimination of the floating body effect resulting from the shorting of the SOI layer and the semiconductor substrate, via use of a storage node capacitor layer.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a DRAM cell, on an SOI layer, incorporating a trench capacitor structure.
It is another object of this invention to use a two dimensional trench capacitor structure, comprised of a vertical trench component, through the SOI layer, through the insulator layer, and into the semiconductor substrate, and a lateral trench component, obtained via undercutting the insulator layer, between the SOI layer and the semiconductor substrate.
It is still another object of this invention to eliminate the floating body effect, encountered with devices fabricated on SOI layers, via the use of a polysilicon layer, on the sides of the trench, shorting the SOI layer to the semiconductor substrate.
In accordance with the present invention a method of fabricating a DRAM cell, on a SOI layer, using a two dimensional trench capacitor structure, and a polysilicon storage node layer, shorting the SOI layer to the semiconductor substrate, is described. A silicon layer overlying an insulator layer, on a semiconductor substrate, is provided. A thin pad silicon oxide layer is formed on the silicon on insulator, (SOI), layer, followed by the creation of a vertical trench, obtained via an anisotropic reactive ion etching, (RIE), procedure, in the pad silicon oxide layer, in the SOI layer, in the insulator layer underlying the SOI layer, and into a portion of the semiconductor substrate. An isotropic, wet etching procedure is employed to widen the trench, in the insulator layer, creating a lateral trench component, in the insulator layer, between the overlying SOI layer, and the underlying semiconductor substrate. A first polysilicon layer is next deposited, at a thickness which allows the first polysilicon layer to only interface the sides of the trench, without completely filling the trench, connecting the SOI layer to the semiconductor substrate. A deposition of a dielectric layer, overlying the first polysilicon layer is next accomplished, followed by the deposition of a second polysilicon layer, overlying the dielectric layer and completely filling the trench. An anisotropic RIE procedure is used to remove the second polysilicon layer, the dielectric layer, and the first polysilicon layer, from areas outside the trench, resulting in the trench capacitor structure comprised of a storage node, formed from the first polysilicon layer, a capacitor dielectric layer, and a cell plate, formed from the second polysilicon layer. Removal of the thin pad oxide layer is followed by the creation of the transfer gate transistor, comprised of a thin gate insulator layer, on the SOI layer, a polysilicon gate structure on the thin gate insulator layer, lightly doped source and drain regions, insulator spacers on the sides of the polysilicon gate structure, and heavily doped source and drain regions.
REFERENCES:
patent: 5176789 (1993-01-01), Yamazaki et al.
patent: 5418177 (1995-05-01), Choi
patent: 5432365 (1995-07-01), Chin et al.
patent: 5585285 (1996-12-01), Tang
patent: 5629226 (1997-05-01), Ohtsuki
Nishihara et al.“A Buried Capacitor Cell with Bonded SOI for 256-Mbit and 1-Gbit DRAMs,” Solid State Technology, Jun. 1994, pp. 89-94.
Eimori et al. “VLSIDRAM/Simox with Stacked Capacitor Cells for Low-Voltage Operation,” IEDM, 1993, pp. 45-48.
Chi Min-hwa
Lu Chih-Yuan
Ackerman Stephen B.
Bowers Charles
Saile George O.
Thompson Craig
Vanguard International Semiconductor Corporation
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