Method for fabricating a dielectric isolated integrated circuit

Details Method for fabricating a dielectric isolated integrated circuit Method for fabricating a dielectric isolated integrated circuit

1984-11-30

1986-02-04

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29578, 29580, 148174, 148175, 148DIG85, 148DIG122, 148DIG26, 156647, 156649, 156653, 156657, 357 49, 357 50, H01L 21302, H01L 2176

Patent

active

045676461

ABSTRACT:
A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, "islands", and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.

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Anantha et al., "High-Voltage Power Transistors", I.B.M. Tech. Discl. Bull., vol. 16, No. 9, Feb. 1974, pp. 2874-2875.

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