Method for fabricating a compound-material wafer

Details Method for fabricating a compound-material wafer Method for fabricating a compound-material wafer

2011-02-22

2011-02-22

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

With measuring or testing

C438S455000, C438S458000, C257SE21568

Reexamination Certificate

active

07892861

ABSTRACT:
The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.

REFERENCES:
patent: 2002/0187595 (2002-12-01), Walitzki et al.
patent: 2006/0024915 (2006-02-01), Kobayashi
patent: 2007/0040181 (2007-02-01), D'Evelyn et al.
patent: 1 566 830 (2005-08-01), None
patent: WO 2004/008527 (2004-01-01), None
M. Kimura et al., XP-000891091 “A New Method for the Precise Measurement of Wafer Roll off of Silicon Polished Wafer”,Japanese Journal of Applied Physics, vol. 38,pp. 38-39 (1999).
C. Maleville et al., XP-002389358, “ SOI: Challenges And Solutions To Increasing Yield In A Ultrathin Age”, Yield Management Solutions, vol. 6, No. 2, pp. 1-84 (2004).

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