Method for fabricating a capacitor of semiconductor memory...

Details Method for fabricating a capacitor of semiconductor memory... Method for fabricating a capacitor of semiconductor memory...

1999-11-23

2001-05-15

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06232133

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a field on fabrication of semiconductor device; and, more particularly, to a method for fabricating a capacitor of semiconductor memory device, which can effectively prevent Ti from diffusing into the ferroelectric layer of capacitor from a Ti adhesive layer, which is formed at the time of metal wiring to decrease the contact resistance between the upper electrode of capacitor and the metal wire.
DESCRIPTION OF THE PRIOR ART
As a non-volatile memory device, A ferroelectric memory device memorizes its stored information even at the time of cutting off power supply and equals to the conventional Dynamic Random Access Memory (DRAM) in view of operating speed. Thus, it is promising as a future generation memory device. Dielectric material of the ferroelectric memory device includes Sr
x
Bi
y
Ta
2
O
9
(hereinafter, referred as SBT), Sr
x
Bi
y
(Ta
1−z
Nb
z
)
2
O
9
(hereinafter, referred as SBTN), Pb(Zr
x
Ti
1−x
) O
3
(hereinafter, referred as PZT). To allow such ferroelectric layer to have excellent ferroelectric characteristics, it is essential to select suitable upper and lower electrodes and to control processes.
Particularly, Ti is used to decrease the contact resistance between the upper electrode of capacitor and metal wire, which connects the upper electrode to a substrate. But, in the case of high integration, the Ti penetrates through the upper electrode and piles up at the boundary between the upper electrode and the ferroelectric layer such as SBTN or SBT. The piled Ti diffuses into a crystalline grain, dipole regions, the boundary between dipole regions and the like in the subsequent thermal treatment. The diffused Ti exists as single element or reacts with oxygen to form fine oxide. Thus, the Ti or Ti oxide plays a role of defect. The defects in the crystalline grains, dipole regions and the boundary between dipole regions prevent polarization to show low polarization characteristics and serve as a path of leakage current rapidly to deteriorate electric characteristics. The Ti also substitutes the Ta or Nb site composed in the layered perovskite structure to break the structure or to deform the structure. This generates polarization fatigue, which rapidly decreases the value of polarization with high frequency applied from the outside.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a capacitor of semiconductor memory device, which can effectively prevent Ti from diffusing into the ferroelectric layer of capacitor through the upper electrode from the Ti layer used as adhesive layer of metal wire.
In accordance with an embodiment of the present invention, there is provided a method for fabricating a capacitor of semiconductor memory device, which comprises the steps of forming a lower electrode of capacitor; forming a ferroelectric layer on the lower electrode; forming an oxide layer as a diffuse barrier on the ferroelectric layer; and forming an upper layer on the oxide layer.
The present invention is characterized in that in order to suppress diffusion of Ti from the Ti adhesive layer formed at the time of metal wire formation process into the inside of the capacitor, a dense oxide layer is formed on the ferroelectric layer such as SBTN or SBT.
The oxide used in the oxide layer of the present invention is preferably the oxide of Ta, or the complex oxide of Ta and Nb. The present invention uses as the Ti barrier oxide, the Ta oxide or Ta/Nb complex oxide, and Ta, Nb and oxygen atoms are the ingredients of STBN or STB used as ferroelectric in the present invention. Thus, the oxide layer used in the present invention can not deteriorate the ferroelectric layer at the subsequent thermal processes although the ingredients of the oxide layer will diffuse into the ferroelectric layer. The ratio of the Ta/Nb complex oxide is preferably in the range of 10:0 and 5:5, more preferably in the range of 10:0 and 7:3, most preferably 7:3. In case that the conditions of the subsequent thermal processes are severe, it is recommended that the ratio of the Ta/Nb oxide is in the range of 10:0 and 7:3, particularly, 7:3 for SBTN.
For example, a dense Ta—Nb oxide layer is formed with a thickness less than 700 Å on the ferroelectric layer. The thickness of the oxide is preferable to be thinner. But, when it is 50 Å below, Ti may penetrate through the oxide layer to the ferroelectric layer. Therefore, the thickness should be 50 Å over. For example, the oxide layer may be formed by the following methods or the like.
The first method comprises performing deposition process with sputtering using Ta—Nb target and performing oxidation process at furnace of oxygen atmosphere. The second method comprises performing spin-on process using metal organic reagent including Ta and Nb and performing nucleus generation and crystal growing process or processes. The third method is to form the oxide layer by chemical vapor deposition using the metal organic source(s). The forth method is to form the oxide layer by low temperature oxidation using plasma activation energy and various reaction gases.
In the present invention, the oxide layer becomes denser by addition of furnace annealing or rapid thermal annealing (RTA) which sufficiently oxidize the layer. Here, the furnace annealing is performed at a temperature of 500° C. to 800° C. The RTA is performed at a temperature of 600° C. to 1100° C.


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