Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2001-11-20
2003-11-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
Reexamination Certificate
active
06649483
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating a capacitor configuration and in particular to a method for fabricating a capacitor configuration in which the integration of ferroelectric capacitors fabricated by a single-step patterning process is possible in a simple manner.
Modern memory devices use elementary memory cells for storing information. The memory cells have a capacitor device or the like as an elementary memory element. The desire for large scale integrated memory devices having a plurality of essentially identical memory cells makes it necessary to apply a capacitor configuration having a plurality of identical capacitor devices on a substrate, which, in particular, is a semiconductor substrate or the like. In this case, on the surface of the substrate which is used as a basis, the surface, if appropriate, is made such that it is correspondingly pre-patterned. In each case a sequence of specific layers or material layers is formed locally at predefined locations for providing a capacitor device. Consequently, at each of these predefined locations on the surface of the substrate, there is produced an individual separate capacitor device as an essentially layered structure and, overall, a corresponding sequence of a plurality of identical capacitor devices which then form the corresponding capacitor configuration of the memory device. This method for constructing the corresponding elementary memory elements in the form of capacitor devices is used in many memory modules, for example RAM (Random Access Memory) modules, in particular in FeRAM memory devices.
In principle, a number of different procedures are conceivable for the application of the individual layers. In so-called multi-step methods, the sequence of the individual material layers is applied to the surface of the substrate used as a basis in each case in a plurality of process steps. On account of the cell enlargements which are known in the case of multi-step methods and have a disadvantageous effect with regard to the highest possible integration density in the memory modules, a procedure has been adopted in which corresponding layer configurations are formed in a single-step method, in particular in the case of the so-called stacked cell principle, in which the layer configuration of the capacitor device is in each case formed directly above assigned circuit configurations formed within the substrate and is not offset laterally with respect thereto as in the case of the so-called offset cell principle.
After the formation of the layer structures, precisely in the single-step method, with regard to the further process steps—for example required annealing steps, external contact-connection to further metallization layers to be applied and the like—known methods encounter problems in preventing damage to the layer structure as a whole or to the individual layers e.g. on account of reactive processes with the process atmosphere—in particular with oxygen—or on account of interactions between the layers, precisely in the lateral region of the layer structure.
Thus, it can happen, for example, that the plug connections applied on the substrate surface are partially oxidized in the process atmosphere, thereby impairing or interrupting a desired electrical contact between a region in the substrate used as a basis and layers of the capacitor. Furthermore, leakage current sources caused by material reconfigurations and/or other reactive or oxidative processes may also be problematic.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a capacitor device on a substrate which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and with which the sequence of layers of the capacitor device can be formed with a particularly high quality and/or yield in a particularly simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a capacitor configuration including at least one capacitor device, the method includes the steps of:
providing a substrate;
applying a sequence of layers on the substrate by using a 2D patterning process wherein the layers of the sequence of layers respectively are applied in an area-covering manner and subsequently patterned with an etching operation in a common process step;
forming the layers of the sequence of layers locally on a surface of the substrate at respective given locations such that a capacitor device is provided; and
filling free intermediate regions of the surface of the substrate with at least one electrically insulating intermediate layer up to a level of a topmost layer of the capacitor device.
The method according to the invention for fabricating a capacitor configuration having at least one capacitor device wherein intermediate regions of the surface of the substrate which remain free are filled with at least a first, at least essentially electrically insulating intermediate layer, in particular in each case at least up to the level of a topmost layer of the capacitor device. By virtue of this measure, at least the lateral areas and edges of the formed sequence of layers of the capacitor device are mechanically covered and thus protected against undesirable mechanical conversion processes, in particular with the process atmosphere during subsequent process steps. Furthermore, what is also achieved by the electrical insulation is that adjacent layer sequences of adjacent capacitor devices do not acquire electrical contact, which is undesired.
Consequently, it is a basic idea of the present invention that, after the formation of the sequence of layers of the capacitor device, at least the lateral regions or edge regions of the layer sequence of the capacitor device are covered by a corresponding intermediate layer applied in the intermediate regions between the capacitor devices and are thus protected against undesirable chemical conversion processes. Consequently, it is possible to prevent, in particular, the situation in which, for example in an oxygen-containing process atmosphere, the bottommost layer is oxidatively attacked from the lateral region and, as a consequence thereof, the contact between the underlying substrate or corresponding conductivity regions of the substrate and the subsequent layer of the capacitor device is interrupted.
In a preferred mode of the method according to the invention, it is provided that a contact layer is applied to and/or patterned onto the at least one intermediate layer at least in regions, in particular in order in each case to be at least electrically contact-connected to the topmost layer of the capacitor device at least in a central or edge-remote region thereof. In this way, it is possible to realize, in particular, an electrical contact-connection of the capacitor device in the form of the sequence of layers and a corresponding connection to the outside world. In this case, the regions on which the contact layer is applied on the first intermediate layer are chosen precisely in such a way as to produce a corresponding circuit configuration of the plurality of capacitor devices of the capacitor configuration.
During the patterning process of the sequence of layers of the capacitor devices, so-called redeposition effects often occur during specific processes. In this case, during material erosion operations, for example, portions of the eroded material are attached and deposited in the region of the surface of the substrate and, in particular, on the edge regions or lateral regions of the sequence of layers of the capacitor devices. These redepositions are also often referred to as fences and can extend from the edge regions or lateral regions of the sequence of layers also out of the plane of the substrate and, in particular, out of the plane of the topmost layer of the sequence of layers of the capacitor device.
In accordance with a particularly preferred embodiment of the method according to the inv
Hartner Walter
Krönke Matthias
Weinrich Volker
Greenberg Laurence A.
Infineon - Technologies AG
Le Thao
Locher Ralph E.
Nelms David
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