Method for fabricating a capacitor

Details Method for fabricating a capacitor Method for fabricating a capacitor

2001-08-31

2003-03-04

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

Reexamination Certificate

active

06528385

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for the fabrication of capacitor and, more particularly, to a method for fabricating a capacitor that is capable of reducing defects incurred during the separation of capacitor.
DESCRIPTION OF THE PRIOR ART
FIGS. 1A
to
1
C are schematic cross-sectional views illustrating a prior art method for the fabrication of capacitor.
As shown in
FIGS. 1A
, an interlayer insulating film
12
is disposed on a semiconductor substrate
11
obtained by a predetermined process, followed by the deposition of an interlayer insulating film
12
that is selectively etched to form a contact hole for a storage node of the capacitor. Next, a conductive layer is disposed on the whole surface including the contact hole, and a storage node contact plug
13
is formed using an etchback process or a chemical-mechanical polishing (CMP) process. Wherein the storage node contact plug
13
is connected to the semiconductor substrate
11
through the contact hole and has a double layered structure.
In an ensuing step, a capacitor oxidation film
14
is formed on the whole surface, including the storage node contact plug
13
, and a mask for defining the capacitor is then formed thereon. Subsequently, the capacitor oxidation film
14
is selectively etched using the mask to thereby expose a portion on which a bottom electrode of the capacitor is to be formed (i.e., a portion to which the storage node contact plug
13
is exposed). Thereafter, the interlayer insulating film
12
and the capacitor oxidation film
14
in a peripheral circuit region II are selectively etched to form an alignment key box pattern
15
.
After the above step, a polysilicon layer
16
, for the bottom electrode is formed on the whole surface including the exposed portion. A mask
17
is disposed thereon through the use of a photosensitive film serving to expose the peripheral circuit region II.
As shown in
FIG. 1B
, the polysilicon
16
in the peripheral circuit region II is etched using the mask
17
, after which a distinct bottom electrode
16
a
is formed using the CMP process. In this case, a photosensitive film
17
a
remains within the contact hole in the bottom electrode
16
a.
As shown in
FIG. 1C
, the photosensitive film
17
a
remaining within the bottom electrode
16
a
is then removed.
The prior art method suffers from a drawback, in that, it employs the chemical mechanical polishing process for the separation of the capacitors, resulting in an excessive height loss of the capacitor and various defects resulting from various causes, e.g., slurry residue, broken portions of the capacitor structure, dishing, and particles, which, in turn, deteriorates the yield of the resulting semiconductor device.
In addition, the prior art method must utilize four distinct pieces of equipment such as equipment for removal of the polysilicon in the peripheral circuit region II, equipment for the chemical-mechanical polishing, equipment for stripping away the photosensitive film and equipment for the wet etch. As a result of the need for these various pieces of equipment and the associated handling, the prior art process suffers from a shortcoming in that it increases the number of defect sources and increases the process time, both of which tend to deteriorate the yield of semiconductor device.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a method for fabricating capacitors that is capable of reducing defects introduced as the result of the complicated process during the separation of capacitor, to thereby enhance the yield of the resulting semiconductor device.
In accordance with a preferred embodiment of the present invention, there is provided a method for the fabrication of capacitor, comprising the steps of: forming an insulating film on a semiconductor substrate in which a cell region and a peripheral circuit region are defined; selectively etching the insulating film, followed by opening a region in which a bottom electrode will be formed; depositing a conductive layer for the bottom electrode on the whole surface, including the opened region; forming a photosensitive film pattern that exposes the peripheral circuit region; removing the conductive layer in the peripheral circuit region using the photosensitive film as a mask; applying an etchback process to the photosensitive film to expose the conductive layer in the cell region; applying an etchback process to the conductive layer until the insulating film covered with the conductive layer is exposed, to thereby form a distinct bottom electrode; and stripping away the remaining photosensitive film.


REFERENCES:
patent: 5597755 (1997-01-01), Ajika et al.
patent: 5895250 (1999-04-01), Wu

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