Method for fabricating a buried Schottky logic array and apparat

Details Method for fabricating a buried Schottky logic array and apparat Method for fabricating a buried Schottky logic array and apparat

1991-02-22

1992-08-18

Jackson, Jr., Jerome

357 34, 357 71, H01L 2956, H01L 2972

Patent

active

051403838

ABSTRACT:
A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a buried perimeter (92) of the metal layer (62). A conductive lead (86) is formed in the Schottky via (68). A poly emitter terminal (46) connects a small sized emitter (50) formed in an epitaxial region (24) to the exterior. Poly emitter (46) presents a large area (76) to the exterior for alignment with a via (66) through a passivating dielectric layer (64), thus alleviating alignment problems.

REFERENCES:
patent: 4258379 (1981-03-01), Watanabe et al.
patent: 4567501 (1986-01-01), Fukuda
patent: 4665414 (1987-05-01), Koeneke et al.

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