Method for extracting a resistor network from an integrated circ

Details Method for extracting a resistor network from an integrated circ Method for extracting a resistor network from an integrated circ

1996-07-12

1999-08-24

Stamber, Eric W.

39550004, 39550005, G06F 1700, G06F 1750

Patent

active

059434872

ABSTRACT:
A method for extracting a reduced resistor network from an integrated circuit polygon layout is disclosed. The polygon layout includes a Manhattan polygon defined by a plurality of boundary lines. The method involves fracturing the Manhattan polygon along first and second division lines which extend from an intersection point at which first and second boundary lines intersect to define a 270 degree angle within the polygon. The first and second division lines extend parallel to the first and second boundary lines respectively and traverse the polygon so as to fracture the polygon into a number of rectangles. Each rectangle is substituted, or modeled, with a star configuration resistor arrangement, so as to construct a full resistor network. The method then enters an iterative sequence in which network reduction opportunities within the full resistor network are identified, and data concerning each network reduction opportunity is stored. The full resistor network is then reduced to a reduced resistor network by performing a series of reduction steps.

REFERENCES:
patent: 5210699 (1993-05-01), Harrington
patent: 5452224 (1995-09-01), Smith, Jr. et al.
patent: 5598348 (1997-01-01), Rusu et al.
Wang et al. "Accurate Parasitic Resistance Extraction for Interconnection Analysis," IEEE, May 1, 1995, pp. 255-258.
"Resistance Extraction from Mask Layout Data," Horowitz, H. Dutton, R.W., IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, pp. 145-150, Jul. 1983.
"An Algorithm for Resistance Calculation from IC Mask Pattern Information," Yoshimura, H. et al., 1979 ISCAS Proceedings, IEEE Catalog No. 79 CH1421-7 CAS, pp. 478-481, Jul. 17-19, 1979.

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