Patent
1995-12-19
1998-11-10
Treat, William M.
395570, 39580023, 395591, G06F 900, G06F 906
Patent
active
058357483
ABSTRACT:
A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
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Bistry David
Dulong Carole
Eitan Benny
Glew Andrew F.
Kowashi Eiichi
Intel Corporation
Treat William M.
Winder Patrice L.
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