Method for evaluating the timing of digital machines with statis

Details Method for evaluating the timing of digital machines with statis Method for evaluating the timing of digital machines with statis

1990-12-21

1994-11-15

Ramirez, Ellis B.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

053654633

ABSTRACT:
An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory). Other enhancements include application enhancements by providing generality of methodology and accommodation of large model size, further computational enhancement by providing generality of delay propagation algorithms and diagnostic enhancements by providing cycle time/yield data and allowance of re-simulation of failure modes of design performance by retaining seed values corresponding to simulated machines.

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