Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-11-14
2003-10-07
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S471000, C438S476000
Reexamination Certificate
active
06630363
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor processing, and more particularly to measuring impurity concentrations of polycrystalline silicon material used as the starting material for growing monocrystalline silicon ingots using the Czochralski (CZ) method.
BACKGROUND OF THE INVENTION
Manufacturers of semiconductor integrated circuits are constantly striving to increase the performance and reduce the price of their products. One way to both increase the performance and reduce the price of an integrated circuit is to reduce the size of the integrated circuit. By reducing the size of a circuit, more circuits can be manufactured on a single semiconductor substrate, thereby reducing the unit cost of the circuit. In addition, reducing the size of a circuit typically increases its speed and reduces its power consumption.
One problem manufacturers encounter in attempting to reduce the size of their integrated circuits involves impurity contamination. For example, metallic contamination of a semiconductor substrate can cause excess leakage currents, poor voltage breakdown characteristics, and reduced minority carrier lifetimes. As the size of an integrated circuit decreases, the detrimental effect of impurities in the semiconductor is magnified. For extremely small circuits, even relatively low levels of contamination can be sufficient to render the circuit inoperative. Therefore, manufacturers take extraordinary measures to prevent impurity contamination in their manufacturing processes.
To optimize their contamination control practices, manufacturers often need to measure the concentration of impurities in their semiconductor substrates at various points during the manufacturing process. This allows manufacturers to determine which area(s) of their process are causing impurity contamination problems. However, as the levels of impurity concentration have decreased to very low levels, it has become more and more difficult to measure the impurity concentration. Indeed, semiconductor industry standards such as the National Semiconductor Roadmap call for impurity concentrations to be as low as 10
10
cm
−3
in the near future. Since the atomic density of a typical semiconductor substrate such as silicon is approximately 10
22
cm
−3
, impurity concentrations of 10
10
cm
−3
can be very difficult to measure even with sophisticated measurement equipment.
For example, copper (Cu) and nickel (Ni) are two metallic impurities found in semiconductor substrates. Impurity concentrations of copper and nickel in heavily boron-doped substrates typically are measured by techniques such as Total Reflection X-Ray Fluorescence (TXRF) and Secondary Ion Mass Spectroscopy (SIMS), etc. The minimum detection limit of copper is approximately 10
17
cm
−3
by TXRF (measured near the surface of the substrate) and approximately 10
15
cm
−3
by SIMS. As a result, manufacturers have begun to search for new ways to measure impurity concentrations in semiconductor substrates.
As acceptable levels of metallic impurities are continually being reduced and new methods for measuring impurity concentrations are developed, manufacturers must understand and control the impurity concentrations of processes used to manufacture semiconductor substrates.
One such area of concern is the initial polycrystalline silicon used to be formed into monocrystalline silicon ingots by the Czochralski (CZ) or Float Zone (FZ) methods.
SUMMARY OF THE INVENTION
The Invention provides a method for evaluating the concentration of impurities within a semiconductor crystal grown using either the Czochralski or the Float Zone technique.
In one embodiment of the invention, a gettering layer is formed on one surface of the moncrystalline sample to getter impurities that have been transferred from the polycrystalline submaterials and crystal pulling equipment to the monocrystalline sample. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations contained within the sample grown.
REFERENCES:
patent: 5233191 (1993-08-01), Noguchi et al.
patent: 6174740 (2001-01-01), Ohta et al.
patent: 2001196433 (2001-07-01), None
Wolf, S. and Tauber, R.N., “Silicon Processing for the VLSI Era”, vol. 1, pp. 5, 8 and 21, 1986.
Anderson Douglas G.
Koveshnikov Sergei V.
Anderson Douglas G.
Novacek Christy
SEH America Inc.
Zarabian Amir
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