Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-01-23
2007-01-23
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S612000, C438S613000
Reexamination Certificate
active
10896808
ABSTRACT:
A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.
REFERENCES:
patent: 5959356 (1999-09-01), Oh
Brady III Wade James
Huynh Andy
Nguyen Thinh T
Tung Yingsheng
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