Method for etching tantalum oxide layer

Details Method for etching tantalum oxide layer Method for etching tantalum oxide layer

1998-05-07

1999-12-14

Kunemund, Robert

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438714, 438720, 438723, H01L 2130

Patent

active

060017422

ABSTRACT:
A method of etching tantalum oxide layer in the fabrication of dynamic random access memory (DRAM). The method comprises the steps of forming the lower electrode structure of a capacitor on a semiconductor substrate. Then, a tantalum oxide layer, a barrier layer and a conductive layer are sequentially formed over the lower electrode structure and the substrate. Next, the conductive layer is patterned using a first reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). Thereafter, the barrier layer is patterned using a second reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). Finally, the tantalum oxide layer is patterned using a third reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2).

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T. Kanniainen, H. Kattelus and J. Skarp, Growth of Dielectric HfO.sub.2 /Ta.sub.0 05 Thin Film Nanolaminate Capacitors by Atomic Layer Epitaxy, pp. 36-46.

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