Etching a substrate: processes – Gas phase etching of substrate – Etching inorganic substrate
Reexamination Certificate
1999-08-06
2002-07-30
Gulakowski, Randy (Department: 1746)
Etching a substrate: processes
Gas phase etching of substrate
Etching inorganic substrate
C438S706000, C438S723000, C438S724000, C438S738000
Reexamination Certificate
active
06426016
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method to etch a passivation layer and an antireflective layer on a substrate, more particularly, to a method of etching a passivation layer and an antireflective layer on a substrate in various etching chambers during a metal contact process of a device.
BACKGROUND OF THE INVENTION
The invention relates to the prevention of pad discolor effect of a metal layer after the etching of passivation layers and an antireflective coating formed thereon.
A metal layer is formed over the whole surface of a substrate composed of a silicon wafer. The metal layer is composed of thin films of Aluminum or thin films of an alloy in which silicon (Si) or Copper (Cu). The surface of the substrate on which the wiring layer is formed is generally covered with an insulating layer composed of SiO
2
, etc. The surface of the substrate or a lower layer of wiring is exposed inside a contact hole provided on a part of the insulating layer. To prevent an increase in contact resistance of an aluminum or aluminum alloy thin film wiring due to an alloy reaction with a silicon wafer, a so-called barrier metal of thin film of Ti, TiN or TiW is provided between the silicon wafer and the aluminum thin film.
Referring to
FIG. 1
, a semiconductor structure
100
is provided and a metal layer
110
is formed on the semiconductor structure
100
. The metal layer
110
is served as metal lines of integrated circuits formed in the semiconductor structure
100
and it will be exposed after passivation layers of integrated circuits are defined for metal contact. After the metal layer
110
is formed on the semiconductor structure
100
, an antireflective layer
120
is formed on the metal layer for reducing reflectivity during following photolithography processes. In general, the antireflective layer
120
is formed of TiN material.
Still referring to
FIG. 1
, a silicon oxide layer
130
is formed on the antireflective layer
120
and a silicon nitride layer
140
is formed on the silicon oxide layer
130
. The composing structure of the silicon oxide layer
130
and the silicon nitride layer
140
is indicated as a passivation layer of integrated circuits fabricated in the semiconductor structure
100
.
After the passivation layer is formed on the antireflective layer
120
, an etching process is performed to expose the portion surface of the metal layer
110
for metal contact or pad contact of integrated circuits. The passivation layer and the antireflective layer
120
are etched in the etching process. In a conventional technique, the etching process is a two-step process and the first step of the etching process is firstly performed to remove the passivation layer, as shown in FIG.
2
. Referring to
FIG. 3
, the antireflective layer
120
is removed from the surface of the metal layer
110
in the second step of the etching process.
In the prior art, the etching of the passivation layer and the antireflective layer
120
is implemented in various chambers. The passivation layer consisting of the silicon nitride layer
140
and the silicon oxide layer
130
is etched in etching equipment, which is called as TEL5000. In the TEL5000 etching equipment, the etching rate of the silicon nitride layer
140
, which is deposited by using a plasma enhanced chemical vapor deposition (PECVD) process, has an uniformity of between about 15% to 75%. Moreover, the etching rate of the silicon oxide layer
130
in TEL5000 has a uniformity of between about 6% to 15%. The etching of the silicon nitride layer
140
and the silicon oxide layer
130
is not uniform enough, because the uniformity of the etching rate of these layers is not good enough. As the passivation layer around the center of the wafer that is the passivation layer deposited thereon is just etched, there is oxide residue at the peripheral regions of the wafer. Furthermore, the layer near the peripheral regions of the wafer is just etched; the silicon oxide layer
130
near the center of the wafer could be damaged.
In other words, the silicon nitride layer
140
and the silicon oxide layer
130
are etched in a single chamber, polymer formed in the chamber during the etching process of the silicon oxide layer
130
is different with that formed during the etching process of the silicon nitride layer
140
. The polymer that formed during the etching process of the silicon nitride layer
140
and the silicon oxide layer
130
will be difficult to form on the walls of the chamber and there becomes a particle issue in following etching processes.
In addition, the uniformity of the etching rate of the passivation layer is not good enough so as that there is silicon oxide residue on the antireflective layer
120
. The silicon oxide residue on the antireflective layer
120
prevents the partial portion of the antireflective layer
120
from etching; the metal layer
110
can not be completely exposed. That is called as pad discolor effect. In general, the antireflective layer
120
is removed in another chamber that is different to the chamber which the passivation layer is etched therein.
Thus, there is a need to etch the silicon nitride layer and the silicon oxide layer of the passivation layer in a uniform etching rate so as to prevent the metal layer under the passivation layer from the pad discolor issue.
SUMMARY OF THE INVENTION
A method to etch a passivation layer and an antireflective layer on a substrate, comprising: forming a metal layer on the substrate; forming the antireflective layer on the metal layer; forming the passivation layers on the antireflective layer, wherein the passivation layer consisting of a silicon oxide layer on the antireflective layer and a silicon nitride layer on the silicon oxide layer; etching the silicon nitride layer in a first etching chamber, wherein the silicon nitride layer is etched in a uniformity of less than 10% in the first etching chamber; etching the silicon oxide layer in a second etching chamber, wherein the silicon oxide layer is etching in a uniformity of less than 5% in the second etching chamber; etching the antireflective layer in the second etching chamber to expose a surface of the metal layer for metal contacts of integrated circuits.
REFERENCES:
patent: 4374698 (1983-02-01), Sanders et al.
patent: 4529476 (1985-07-01), Kawamoto et al.
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5658425 (1997-08-01), Halman et al.
patent: 5846880 (1998-12-01), Lee
patent: 5872062 (1999-02-01), Hsu
patent: 5961791 (1999-10-01), Frisa et al.
patent: 5970373 (1999-10-01), Allen
patent: 6117351 (2000-09-01), Li et al.
Chen Hwang-Ming
Lin Hu-Ching
Wang Chang-Hsien
Yang Cheng-Jui
Ahmed Shamim
Gulakowski Randy
Mosel Vitelic Inc.
Nath&Associates PLLC
Novick Harold L.
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