Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2001-05-15
2002-09-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S905000
Reexamination Certificate
active
06451620
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for etching an organic film, a method for fabricating a semiconductor device and a pattern formation method.
2. Description of the Related Art
For the purpose of increasing the operation speed and lowering the consumption power of semiconductor devices, decrease of the dielectric constant of an interlayer insulating film included in a multi-level interconnect structure is recently regarded as significant. In particular, an organic film with a small dielectric constant can be easily formed by spin coating and curing, and hence is regarded as a very promising interlayer insulating film of the next generation. A well known example of the organic film with a small dielectric constant is an organic film including an aromatic polymer as a base.
In order to fabricate a device with a refined design rule of a gate length of 0.18 &mgr;m or less, a fine interconnect processing technique of approximately 0.25 &mgr;m or less is necessary, and the design rule is considered to be more and more refined in the future. An organic film is generally patterned by plasma etching, but a fine pattern of 0.25 &mgr;m or less is very difficult to form from an organic film.
Known examples of the plasma etching employed for an organic film are a process using an etching gas including a N
2
gas and a H
2
gas as principal constituents (reported by M. Fukusawa, T. Hasegawa, S. Hirano and S. Kadomura in “Proc. Symp. Dry Process”, p. 175 (1998)) and a process using an etching gas including a NH
3
gas as a principal constituent (reported by M. Fukusawa, T. Tatsumi, T. Hasegawa, S. Hirano, K. Miyata and S. Kadomura in “Proc. Symp. Dry Process”, p. 221 (1999).
CONVENTIONAL EXAMPLE 1
One of conventional etching methods will now be described as Conventional Example 1 referring to the result obtained by etching an organic film with a magnetic neutral loop discharge (NLD) plasma etching system manufactured by ULVAC JAPAN, Ltd. (“SiO
2
Etching in magnetic neutral loop discharge plasma”, W. Chen, M. Itoh, T. Hayashi and T. Uchida, J. Vac. Sci. Technol., A16 (1998) 1594).
In Conventional Example 1, an organic film is etched by using an etching gas including a N
2
gas and a H
2
gas as principal constituents. The present inventors have carried out the etching process of Conventional Example 1 under the following conditions:
Plasma etching system: NLD plasma etching system
Volume flow ratio per minute in standard condition of etching gas:
N
2
:H
2
=50 ml:50 ml
Antenna power: 1000 W (13.56 MHz)
Bias power: 200 W (2 MHz)
Pressure: 0.4 Pa
Substrate cooling temperature: 0° C.
Etching time: 180 seconds
FIGS. 16A through 16D
are cross-sectional SEM photographs of holes formed under the aforementioned etching conditions in organic films, and the holes of
FIGS. 16A through 16D
have diameters of 0.16 &mgr;m, 0.18 &mgr;m, 0.24 &mgr;m and 0.40 &mgr;m, respectively. In
FIGS. 16A through 16D
, a reference numeral
101
denotes a silicon substrate, a reference numeral
102
denotes an organic film to be etched, and a reference numeral
103
denotes a mask pattern of a silicon oxide film used as a mask in etching the organic film
102
. The organic film
102
has a thickness of approximately 1.02 &mgr;m, and the mask pattern
103
has a thickness of approximately 240 nm.
CONVENTIONAL EXAMPLE 2
In a multi-level interconnect structure of a semiconductor device, a lower interconnect, an interlayer insulating film and an upper interconnect are successively stacked, and the lower interconnect and the upper interconnect are connected to each other through a pillar-shaped plug formed in the interlayer insulating film. Also, single damascene and dual damascene methods have recently been developed. In the single damascene method, a via hole or an interconnect groove is formed in an interlayer insulating film and is subsequently filled with a metal material, so as to form a connection plug or a metal interconnect. In the dual damascene method, a via hole and an interconnect groove are formed in an interlayer insulating film and are subsequently filled with a metal material, so as to simultaneously form a connection plug and a metal interconnect.
Now, the conventional single damascene method will be described as Conventional Example 2 with reference to
FIGS. 17A through 17E
and
18
A through
18
D.
First, as is shown in
FIG. 17A
, a laminated metal interconnect consisting of a first barrier metal layer
212
, a metal film
213
and a second barrier metal layer
214
is formed on a semiconductor substrate
211
. Then, as is shown in
FIG. 17B
, an organic film
215
is formed on the metal interconnect, and thereafter, a silicon oxide film
216
is formed on the organic film
215
as is shown in FIG.
17
C.
Then, a resist pattern
217
is formed on the silicon oxide film
216
by a known lithography technique as is shown in FIG.
17
D. Thereafter, the silicon oxide film
216
is subjected to plasma etching (dry etching) using the resist pattern
217
as a mask, so as to form a mask pattern
216
A from the silicon oxide film
216
as is shown in FIG.
17
E.
Next, the organic film
215
is etched by the method for Conventional Example 1 by using the mask pattern
216
A, so as to form a recess
218
for a via hole or an interconnect groove in the organic film
215
as is shown in FIG.
18
A. Since the resist pattern
217
is formed from an organic compound, it is removed during the etching of the organic film
215
.
Subsequently, a third barrier metal layer
219
of TiN or TaN with a small thickness is formed on the wall of the recess
218
by sputtering as is shown in FIG.
18
B.
Then, the recess
218
is filled with a conducting film
222
by chemical vapor deposition (CVD) or plating as is shown in
FIG. 18C
, and a portion of the conducting film
222
formed outside the recess
218
is removed by chemical mechanical polishing (CMP). Thus, a connection plug or metal interconnect
223
is formed as is shown in FIG.
18
D.
CONVENTIONAL EXAMPLE 3
The conventional dual damascene method will now be described as Conventional Example 3 with reference to
FIGS. 19A through 19D
,
20
A through
20
C and
21
A through
21
C.
First, as is shown in
FIG. 19A
, a lower laminated metal interconnect consisting of a first barrier metal layer
232
, a metal film
233
and a second barrier metal layer
234
is formed on a semiconductor substrate
231
. Then, a first organic film
235
is formed on the lower metal interconnect as is shown in
FIG. 19B
, and a first silicon oxide film
236
is formed on the first organic film
235
as is shown in FIG.
19
C.
Next, a first resist pattern
237
having an opening for a via hole is formed on the first silicon oxide film
236
by a known lithography technique as is shown in FIG.
19
D. Then, the first silicon oxide film
236
is subjected to plasma etching (dry etching) by using the first resist pattern
237
as a mask, so as to form a first mask pattern
236
A from the first silicon oxide film
236
and remove the first resist pattern
237
as is shown in FIG.
20
A. Thereafter, a top face of the first mask pattern
236
A is cleaned so as not to damage the first organic film
235
.
Then, as is shown in
FIG. 20B
, a second organic film
238
is formed on the first mask pattern
236
A, and a second silicon oxide film
239
is formed on the second organic film
238
.
Next, as is shown in
FIG. 20C
, a second resist pattern
240
with an opening for an interconnect groove is formed on the second silicon oxide film
239
. Thereafter, the second silicon oxide film
239
is etched by using the second resist pattern
240
as a mask, so as to form a second mask pattern
239
A from the second silicon oxide film
239
as is shown in FIG.
21
A.
Subsequently, the second organic film
238
and the first organic film
235
are etched by the method for Conventional Example 1, so as to form an interconnect groove
241
by transferring the second mask pattern
239
A onto the second organic film
238
and form a via hole
242
Hayashi Toshio
Morikawa Yasuhiro
Nakagawa Hideo
Matsushita Electric - Industrial Co., Ltd.
Nelms David
Nhu David
Nixon & Peabody LLP
Studebaker Donald R.
LandOfFree
Method for etching organic film, method for fabricating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for etching organic film, method for fabricating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for etching organic film, method for fabricating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2817669