Method for etching memory gate stack using thin resist layer

Details Method for etching memory gate stack using thin resist layer Method for etching memory gate stack using thin resist layer

1998-07-17

1999-11-02

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

257315, H01L 310232, H01L 29788

Patent

active

059776013

ABSTRACT:
A memory gate stack in a high density memory core has spaces on the order of less than 0.25 microns using conventional deep ultraviolet (DUV) lithography techniques by depositing a layer of silicon oxynitride over a plurality of layers, and a thin resist layer overlying on the silicon oxynitride layer. The resist layer has a thickness sufficient to withstand removal during etching of the silicon oxynitride layer, for example about 3,000 Angstroms to about 4,000 Angstroms. The silicon oxynitride layer has a sacrificial portion having a thickness at least about 500 Angstroms, and a stop-layer thickness, used for spacer formation following etching of the memory gate, of at least 1,000 Angstroms. The use of silicon oxynitride as an antireflective coating layer in combination with the thin resist optimizes the resolution of DUV lithography, enabling formation of spacers having widths less than about 0.24 microns. In addition, the sacrificial layer of the silicon oxynitride layer enables self-aligned etching of the plurality of layers to form the memory gate stack, while maintaining sufficient thickness for spacer formation.

REFERENCES:
patent: 4997518 (1991-03-01), Madokoro
patent: 5011782 (1991-04-01), Lamb et al.
patent: 5858879 (1999-01-01), Chao et al.

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