Method for etching layers on a semiconductor wafer in a single e

Details Method for etching layers on a semiconductor wafer in a single e Method for etching layers on a semiconductor wafer in a single e

1998-07-17

2000-12-12

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438719, 438721, 438723, 438738, H01L 21302, H01L 21461

Patent

active

061598607

ABSTRACT:
Polysilicon and oxide layers on a semiconductor wafer are etched in a single etching chamber configured for selectively providing a first etching environment in the chamber for etching of the polysilicon layer, and a second etching environment in the chamber for etching the oxide layer. The decoupled plasma source polysilicon etch chamber enables etching of both oxide-based layers and silicon-based layers, without removing the semiconductor wafer from the etching chamber.

REFERENCES:
patent: 5094712 (1992-03-01), Becker et al.
patent: 5169487 (1992-12-01), Langley et al.
patent: 5201993 (1993-04-01), Langley
patent: 5346586 (1994-09-01), Keller
patent: 5378311 (1995-01-01), Nagayama
patent: 5795829 (1998-08-01), Shen
patent: 5897354 (1999-04-01), Kachelmeier

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