Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-10-01
2001-10-09
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S067000, C216S079000, C257S635000, C257S640000, C257S665000, C438S724000, C438S738000, C438S740000
Reexamination Certificate
active
06300252
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for opening fuse windows in semiconductor devices and more particularly, relates to a method for opening fuse windows in semiconductor devices by a two-step etching process in which a PE oxide and PE nitride layers are first etched away in a first etching step and then multiple layers of inter-metal dielectric materials are etched away in a second etching step which stops at a silicon nitride etch-stop layer.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, conductive fusible links (or fuses) are frequently used to repair any defects in the circuits. Integrated circuits that frequently utilize these conductive fusible links include memory devices such as dynamic random access memory devices (DRAM), static random access memory devices (SRAM) or logic devices. In one method, the conductive fusible links can be made non-conductive by blowing the fuse with the application of laser energy. The fuses are blown so that electrical circuits can be rewired to replace defective devices with redundant circuits. The process of blowing the fuses by the application of laser energy is known as a laser trimming process.
For instance, in a DRAM or SRAM, defective memory cells in the array can be replaced by blowing the fuses associated with the defective cells and thus activating redundant circuits provided in a spare row or column of cells. The technique of using conductive fusible link to repair defective circuits greatly enhances the yield of semiconductor circuits and reduces overall fabrication costs.
Conductive fusible links are also used in logic circuits for repair or reconfiguration by blowing fuses. For instance, it is possible to fabricate a generic logic device which has a large number of interconnected logic gates and then, in a final processing step, the device is customized to perform a specific logic function by disconnecting the unnecessary logic elements by blowing the fuses that make the necessary connections.
The reliability of the fuse blowing technique is important if the yield of IC devices is to be increased. It is especially important when a large number of fuses must be successively blown to achieve a desirable circuit. Limiting factors in the successful blowing of fuses are the minimum laser energy required to blow the fuses and the accessability of the fuses through the fuse window openings provided on the integrated circuit chip. Since fuses are normally formed over thick field oxide regions in a semiconductor substrate for preventing shortening of the fuse to the substrate, the fuse must also be covered by layers of insulating materials to insulate from other conductive layers built on top of the semiconductor device. For instance, in a DRAM device, multiple-level metal conductors are normally used to provide electrical connections in the circuits. Each of the conductive metal layers is insulated by a dielectric material which also covers the fuse that was originally formed on the substrate.
A fuse can be formed of a metal, a polysilicon or a polycide. For instance, metals of aluminum, platinum silicide, titanium and tungsten are frequently used, so are polycides of titanium polycide, tungsten polycide or molybdenum polycide. The dielectric layers used in a memory device can be an insulating layer or a passivation layer formed of borophosphosilicate glass (BPSG), borosilicate glass (BSG), spin-on-glass (SOG), silicon oxide or silicon nitride.
In order to successfully blow a fuse, an opening over the fuse (or a fuse window opening) must be provided in the area where the fuse will be blown so that a laser beam can be effectively used to heat the fuse. For instance, an opening can be made which normally has a width of 4~7 microns and a length of 4~7 microns. Since a use is covered by layers of dielectric materials which impede the laser blowing process by reducing the energy level that actually reaches the fuse, the layers dielectric materials must be etched away or otherwise removed so that the fuse is substantially exposed. Alternatively, a thin layer of a dielectric material can be left on the fuse to protect it from contamination. For a fuse to successfully absorb heat from laser irradiation and thus be blown, the laser trimming process requires that only a very thin dielectric layer covers the fuse such that laser can readily penetrates the dielectric layer and melts the fuse. It is therefore an important aspect of the fuse blowing process that a fuse window must be properly opened through several insulating layers such as silicon nitride, silicon oxide, spin-on-glass and borophosphosilicate glass.
A typical fuse window opening process for a memory device is shown in
FIGS. 1 and 2
. Memory device
10
is built on a semiconductor substrate
12
which has a dielectric layer
14
formed thereon. The semiconductor substrate
12
can be suitably made of silicon and the dielectric layer can be typically a grown or deposited silicon dioxide. A conductive fusible link
16
is formed on the dielectric layer
14
by first depositing a conductive layer such as metal, polysilicon or polycide and then patterning it by known techniques in the art. The fusible link
16
can be a chosen target area of a metal runner that has the same geometry as the rest of the runner or alternatively, the fusible link
16
can be a portion of a runner that has reduced cross-sectional area for improved blowing or melting by laser irradiation. A fusible link of reduced thickness in the region of the fuse opening
22
may be desirable to maximize the laser melting efficiency.
On top of the fusible link
16
, a dielectric layer
18
which is typically a flowable glass material such as BPSG is then deposited. The dielectric layer may also be suitably formed by spin-on-glass or deposited from tetraethoxysilane (TEOS), silane (SiH
4
) or dichloiosilane (SiCl
2
H
2
) by a chemical vapor deposition technique. The dielectric layer
18
is known as a inter-level dielectric (ILD) layer. A first level metal conductor
24
is then formed on the ILD layer
18
by deposition and patterning. In a typical CMOS integrated circuit, the first level metal
16
may be formed of a thickness of approximately 5,000 Å with the ILD layer
18
formed of a phosphorus doped TEOS in a thickness of 6,000 Å over the fusible link
16
.
After a third dielectric layer
26
is formed and planarized, a second metal layer
28
is deposited and patterned similarly as the first metal layer
24
. A passivation layer
32
normally formed of a flowable glass material for ease of planarization is then deposited to insulate the second metal layer
28
.
In the next step of fabrication of the fuse window opening
22
, a thin photoresist layer
34
is deposited over the passivation layer
32
and then patterned by conventional lithographic techniques to expose a bond pad
30
and the fusible link
16
. This is shown in FIG.
2
. The etching process can be conducted by a dry etching technique of reactive ion etching. The photoresist layer
34
serves as an etch mask to prevent etching of the ILD layer
26
from regions adjacent to the fusible link
16
. After the completion of the reactive ion etching process, the photoresist etch mask
34
is removed by a conventional method.
In a typical IC structure such as that shown in
FIGS. 1 and 2
, two or more metal layers
24
,
28
(M
1
, M
2
, etc.) are fabricated on the die to provide patterns of conductive lines. The layers are separated by the dielectric layer
26
. The ILD layer
26
normally overlies the M
1
layer
24
, while the M
2
layer
28
overlies the ILD layer
26
. A topmost passivation layer
32
is typically applied over the M
2
layer
28
. Openings through the passivation layer
32
, shown in
FIG. 2
, expose areas of the M
2
layer
28
as bond pads
30
.
In modern memory devices, the technique of building multi-level metal interconnections is one of the limiting factors in down-sizing integrated circuits. By using more than two metal level, i.e., three or four levels of
Hung Shu-Chi
Ying Shulan
Powell William A.
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
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