Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-12-20
2004-11-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S043000, C438S701000, C438S713000
Reexamination Certificate
active
06818564
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for etching a tapered bore into a silicon substrate from a first face thereof, and the invention also relates to a semiconductor wafer comprising a substrate layer having a tapered bore therein.
BACKGROUND TO THE INVENTION
Micro-machined components formed in a silicon device layer of a semiconductor wafer, in general, are formed in a relatively thin silicon device layer, which is supported on a handle layer. The device layer in which the micro-machined components are to be formed is laminated to the handle layer, which. In general, is also of silicon. In general, an oxide layer is formed between the handle layer and the device layer. The handle layer provides support to the relatively thin device layer within which the micro-machined components are formed. The oxide layer forms an electrical insulation barrier between the device layer and the handle layer. In general, it is necessary to be able to access such micro-machined components through the handle layer, and this requires the formation of access bores extending through the handle layer to the respective micro-machined components. In general, it is desirable that the access bores to such micro-machined components should be accurately aligned with the corresponding one of the micro-machined components, and additionally, it is desirable that the access bores should be accurately dimensioned, and in particular, the transverse cross-sectional area of such bores should be of accurate dimensions. For example, where it is desired to terminate an optical fibre extending through an access bore adjacent the corresponding micro-machined component, it is important that as well as being accurately aligned with the micro-machined component, the access bore should be accurately dimensioned in order to positively and accurately secure and locate the optical fibre relative to the micro-machined component. It is also desirable that such access bores be dimensioned to form a relatively tight fit around to the corresponding optical fibre in order that when the optical fibre is tightly located in the access bore, t e terminal end of the optical fibre is accurately aligned with the micro-machined component. In general, axial alignment of such access bores relative to the corresponding micro-machined component can be achieved without too much difficulty. However, the etching of such access bores of relatively accurate dimensions, particularly relatively accurate cross-sectional dimensions, presents considerable difficulties, and thus subsequent alignment problems when locating the optical fibre in the access bore relative to the micro-machined component.
Additionally, due to the fact that the optical fibre should be a relatively tight fit, and preferably, an interference fit in the access bore. It is desirable that a tapered lead in should be provided to the bore for facilitating initial insertion of the optical fibre into the access bore. This also is difficult to achieve with any degree of accuracy.
In known methods for forming such access bores, an anisotropic wet etch is used where the etchant may, for example, comprise a mixture of potassium hydroxide, isopropylalcohol and water. In general. It is difficult to control the cross-sectional shape of an access bore in such wet etch processes. In particular, it is difficult to wet etch such access bores of regular circular cross-section. This is due to the fact that wet etches tend to etch along the crystalline plane of silicon, and typically, attempts to etch bores of circular cross-section tend to result in bores of square or rectangular cross-section. This is so irrespective of the etch opening formed in a mask through which the etchant is being directed at the silicon.
There is therefore a need for a method for etching a bore, and in particular, a tapered bore into a silicon substrate which overcomes these problems.
The present invention is directed towards providing such a method, and the invention is also directed towards providing a semiconductor wafer comprising a substrate layer having a bore etched therein by the method according to the invention.
SUMMARY OF THE INVENTION
According to the invention there is provided a method for etching a bore into a silicon substrate from a first face thereof, the method comprising the steps of:
forming a masking layer on the first face,
patterning the masking layer to define an etch opening at a location corresponding to the location at which the bore is to be etched into the silicon substrate,
subjecting the silicon substrate to a first dry etch through the etch opening for forming the bore to a first depth, the bore tapering inwardly from the first face to the first depth,
subjecting the silicon substrate to a second dry etch through the etch opening on completion of the first etch for etching the bore to a second depth which is a greater distance from the first face than the distance of the first depth from the first face.
In one embodiment of the invention the transverse cross-sectional area of the portion of the bore extending between the first and second depths formed by the second etch is constant.
In another embodiment of the invention the portion of the bore tapers from the first face to the first depth to be of transverse cross-sectional area adjacent the first depth similar to the transverse cross-sectional area of the portion of the bore extending between the first and second depths at the first depth.
In a further embodiment of the invention the portion of the bore extending between the first face and the first depth, and the portion of the bore extending between the first depth and the second depth are of circular transverse cross-section.
In one embodiment of the invention the portion of the bore extending between the first face and the first depth tapers to define an included cone angle in the range of 30° to 90°.
In another embodiment of the invention the portion of the bore extending between the first face and the first depth tapers to define an included cone angle in the range of 35° to 60°.
In a further embodiment of the invention the portion of the bore extending between the first face and the first depth tapers to define an included cone angle of approximately 40°.
In one embodiment of the invention the area of the etch opening is less than the transverse cross-sectional area of the portion of the bore extending between the first and second depths at the first depth thereof. Preferably, the area of the etch opening is in the range of 80% to 90% of the transverse cross-sectional area of the portion of the bore extending between the first and second depths adjacent the first face of the silicon substrate. Advantageously, the area of the etch opening is approximately 85% of the transverse cross-sectional area of the portion of the bore extending between the first and second depths at the first depth thereof.
Preferably, the shape of the etch opening is of shape similar to the shape of the portion of the bore extending between the first and second depths at the first depth thereof.
In one embodiment of the invention the first and second etches are carried out in a controlled environment chamber.
In another embodiment of the invention the first etch is an isotropic etch.
In a further embodiment of the invention fluorine radicals are created in the controlled environment chamber during the first etch for reacting with the silicon substrate for releasing volatile by-products for forming the portion of the bore extending between the first face and the first depth. Preferably the first etch is carried out with an etchant preparation comprising sulphur hexafluoride. Advantageously, the pressure within the controlled environment chamber is maintained in the range of 5×10
−6
bar to 2×10
−4
bar during the first etch, and the DC bias voltage on the platen is controlled by maintaining input power to the platen in the range of 0 watts to 50 watts. Ideally, the pressure within the controlled environment chamber is maintained at approximately 7×10
&
Analog Devices Inc.
Fourson George
Gauthier & Connors LLP
Maldonado Julio J.
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