Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-11-13
2004-02-10
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000, C134S001100, C134S001200
Reexamination Certificate
active
06689698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of failure analysis in semiconductor manufacturing. Specifically, the present invention relates to removing a silicide poly in a sample preparation for failure analysis in semiconductor manufacturing.
2. Related Art
Failure analysis and sample preparation is an important step in providing a detailed inspection of the physical characteristics of an integrated circuit (IC) fabricated on a semiconductor chip (IC chip). More particularly, proper preparation of the IC chip is an important issue when inspecting the gate oxide region for failure analysis.
However, silicide application in sub-quarter micron ultra large scale integration (ULSI) technology poses a major problem in the analysis of gate oxide failures. Typical construction of the IC chip with a silicide application includes a gate oxide layer under a polysilicon gate layer. The silicide layer covers the underlying polysilicon gate and gate oxide layer.
Previous methods for removing the silicide poly also removed or attacked the underlying gate oxide layer, which was the focus of the failure analysis. For example, in a wet etching method using hydrofluoric (HF) acid, the HF acid readily removes the silicide layer. However, the HF acid also seriously undercuts the underlying gate oxide layer, thus compromising any attempts at failure analysis of the gate oxide layer.
One solution for removing the silicide layer is provided for in a chlorine-based reactive ion etching system (Cl-based RIE). However, the high toxicity of chlorine creates system related problems, such as, safety concerns, increased cost for toxic removal and disposal costs, environmental concerns due to the toxicity of chlorine, etc. Specifically, the typical RIE system does not accommodate use of a Cl-based RIE process. This requires the use and added cost of a specialized chamber for using chlorine in the Cl-based RIE process.
Similarly, a sodium hydroxide (NaOH) solution provides for etching of the polysilicon gate layer with good selectivity of the gate oxide layer, that is the gate oxide layer remains unaffected by the NaOH solution. However, the NaOH solution is ineffective for removing the silicide layer which covers the polysilicon gate layer. As such, only using NaOH for sample preparation is ineffective in exposing the gate oxide layer for failure analysis.
Alternatively, using a lapping process to remove the silicide layer could expose the polysilicon gate layer for etching with a NaOH solution. However, the uneven features of lapping processes typically used in failure analysis labs make the NaOH etching of the polysilicon gate layer non-uniform over the entire ULSI integrated circuit.
Thus, a need exists for a method to provide for clean removal of the silicide layer and the underlying polysilicon gate layer for gate oxide defect characterization. Another need exists for a method using less-toxic materials for increased safety and profitability.
SUMMARY OF THE INVENTION
The present invention provides a method for the clean removal of a cobalt silicide layer and the underlying polysilicon gate layer for gate oxide defect characterization. Also, the present invention provides a method that achieves the above accomplishment and which also provides for increased safety and increased profitability through the use of less-toxic materials.
Specifically, one embodiment discloses a method for exposing a gate oxide layer that includes de-layering the IC chip to the metal-1 (M−1) layer located just above the semiconductor device that includes the cobalt silicide layer. The M−1 layer is removed using a parallel lapping process typically used in failure analysis laboratories.
In another embodiment, the present invention discloses a method for exposing a gate oxide layer with a fluorine based reactive ion etching (F-based RIE) process and immersion in a sodium hydroxide based solution. The F-based RIE damages a cobalt silicide layer that covers a polysilicon gate layer, and creates a multitude of pinholes in the silicide layer. Pinholes in the cobalt silicide layer allow for penetration of chemicals into the polysilicon gate layer. Immersion of the IC chip in the sodium hydroxide based solution etches away the polysilicon gate layer and lifts off the cobalt silicide layer without altering an underlying gate oxide layer. As such, failure analysis of the gate oxide layer can proceed without concern for damage due to the removal process.
In one embodiment of the present invention, the solution of sodium hydroxide is heated to approximately 50° C. to 55° C. before immersing the sample in the solution. After immersion, the sample is rinsed in de-ionized water and blown dry to complete the sample preparation.
Additionally, another embodiment uses a solution including sodium hydroxide (NaOH) and sodium chloride (NaCl) for balancing the etching rates for p-type and n-type polysilicon gate layers. This solution of NaOH and NaCl is most useful in ULSI technologies of 0.15 micrometers or below 0.15 micrometers.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
patent: 3791848 (1974-02-01), DeAngelo
patent: 6147002 (2000-11-01), Kneer
patent: 6284662 (2001-09-01), Mikagi
patent: 6495394 (2002-12-01), Nakata et al.
Redkar Shailesh
Rong Guo Zhi
Younan Hua
Zhigang Song
Chartered Semiconductor Manufacturing Limited
Norton Nadine G.
Vinh Lan
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