Dynamic magnetic information storage or retrieval – General processing of a digital signal – Data clocking
Reexamination Certificate
1999-05-06
2001-02-20
Tran, Thang V. (Department: 2753)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Data clocking
C360S046000
Reexamination Certificate
active
06191906
ABSTRACT:
RELATED APPLICATION(S)
Not applicable
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
TECHNICAL FIELD
This invention relates to disk drive data storage devices and more particularly to a high-speed phase estimating method for improving signal acquisition performance in a disk drive read channel.
BACKGROUND OF THE INVENTION
Conventional disk drives have employed peak detection techniques to recover digital data written as saturation recording onto a magnetizable surface media of a rotating disk. Using peak detection requires spacing flux transitions sufficiently apart so that analog peaks in the recovered data stream may be identified and the corresponding data recovered. To achieve reasonable bandwidths in data channels, it has been customary to employ data coding techniques, such as a (1,7) RLL code in which flux transitions are no closer together than every other clock bit time period (“bit cell”) nor farther apart than eight clock bit cells. Such codes are referred to as “rate two-thirds” codes because two data bits are coded into three code bits. Thus, with a rate two-thirds code, one third of the user storage area of the storage disk is required for code overhead.
One way of decreasing the code overhead is to employ a code in which flux transitions are permitted in adjacent bit cells, such as a (0,4,4) code, which is referred to as a rate eight-ninths code in which nine code bits are required for eight incoming data bits. Using such a code significantly increases the disk data storage capacity, but causes flux transitions to occur in adjacent bit cells, which results in intersymbol interference (“ISI”). Unfortunately, peak detection techniques are not effective or reliable in recovering data coded in an eight-ninths code format, such as (0,4,4).
However, partial response signaling enables improved handling of ISI and allows more efficient use of a given channel bandwidth. Because the nature of ISI is known in these systems, it may be taken into account in the decoding/detection process. Partial response data transmission lends itself to synchronous sampling and provides an elegant compromise between error probability and the available spectrum. Partial response systems include duobinary, dicode, and class IV (or “PR
4
”) systems. The PR
4
system emphasizes midband frequencies and results in a read channel having increased noise immunity and reduced distortion at both low and high frequencies. In magnetic recording PR
4
is a preferred partial response system because its response spectrum closely matches the natural characteristics of a magnetic data write/read channel.
Detecting user data from a stream of coded data requires shaping the channel to a desired partial response characteristic, such as the PR
4
characteristic, and employing a maximum likelihood (“ML”) sequence estimation technique. The maximum likelihood sequence estimation technique extracts the data by analyzing a number of consecutive data samples from the coded serial data stream, rather than sampling just one peak, as was done with prior peak detection methods.
One ML sequence estimation algorithm is the well-known Viterbi detection algorithm. Application of the Viterbi algorithm to PR
4
data streams within a magnetic recording channel improves data detection performance in the presence of ISI and improves the signal-to-noise ratio over other peak detection techniques. Because the Viterbi algorithm operates on a sequence of discrete data samples, the read signal is necessarily filtered, sampled, and equalized.
Disk drive data capacity and performance has also been improved by employing techniques, such as zoned data recording, embedded servo sector-based head positioning, and thin-film heads. However, these improvements were somewhat incompatible with PR
4
,ML data detection techniques because the resulting coded serial data stream had rapidly varying gain, frequency, and phase that inhibited predictable signal sampling. Accordingly, prior workers have developed rapidly acting gain, frequency, and phase timing acquisition control loops within the PR
4
,ML data channel so that the phase of the sampling clock could be rapidly resynchronized following interruption by an embedded servo sector, or upon switching from one data zone to another. Disk drives employing such techniques are described in U.S. Pat. No. 5,341,249 for DISK DRIVE USING PMRL CLASS IV SAMPLING DATA DETECTION WITH DIGITAL ADAPTIVE EQUALIZATION, which is assigned to the assignee of this application and is incorporated herein by reference.
Unfortunately, as disk drive capacity and performance continues to increase, even the above-described acquisition control loops are being taxed to their limits. In addition to performance, disk drives are diminishing in size and cost. Accordingly, higher performance must be accompanied by simplification and cost reduction.
SUMMARY OF THE INVENTION
An object of this invention is, therefore, to provide a very high performance data acquisition control loop.
Another object of this invention is to simplify existing disk drive control loops while improving their performance.
A further object of this invention is to provide a method of estimating the phase angle between two signals.
A multi-mode timing loop of this invention combines an analog-based timing loop and a digital timing loop for timing data samples taken by a flash analog-to-digital A/D converter. During a non-read mode, timing is controlled by the analog based timing loop, and during read mode, timing is controlled by the digital timing control circuit. During non-read mode, a frequency synthesizer generates predetermined frequencies approximately corresponding to expected disk drive data rates. The synthesizer also generates a clock signal that enters a phase detector for comparison with the flash A/D converter sampling clock signal provided by a current-controlled oscillator.
Read mode is entered whenever user data is read from the disk surface. The beginning of every recorded data segment has a data header that includes a constant frequency preamble pattern that is used to initialize gain settings, preset the timing loop to an approximate starting phase, and synchronize the sampling clock in preparation for sampling subsequent user data. When the preamble pattern is first detected, a timing acquisition mode is entered, during which the flash A/D converter samples the incoming waveform at approximate locations. During the timing acquisition mode, the digital timing loop is in control, which has various components including a timing error extractor. Data samples are conveyed from the flash A/D converter to the timing error extractor, which generates sampling phase estimates for approximately phase locking the loop until adaptive components in the loop can settle.
The timing error extractor preferably employs a phase estimating approach that determines the phase angle between the sampled input signal and the sampling clock by computing arctan(v/u)=arctan(alog(log(v)−log(u)), where (v) and (u) are the respective quadrature amplitudes of the input signal and the sampling clock. The log function values are stored in a first lookup table that is time-shared by a switching function to provide both the log(v) and log(u) values. A storage element holds the log(u) value while the switching function routes magnitude v to the first lookup table.
The resulting log(v) value and the stored log(u) are combined in a subtraction function that generates log(v)−log(u), which result addresses a second lookup table that returns the addressed arctan(alog(log(v)−log(u)) value.
The phase estimating approach of this invention is advantageous because it is insensitive to gain, does not include a costly and time-consuming divide operation, and does not require an unduly large lookup table. Such an approach may be readily implemented in an application specific integrated circuit.
REFERENCES:
patent: 5341249 (1994-08-01), Abbott et al.
Neal Regina Y.
Quantum Corp.
Stolowitz Micah
Tran Thang V.
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