Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2006-07-11
2006-07-11
Teska, Kevin J. (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S013000, C703S014000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07076405
ABSTRACT:
The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of stages. (1) At the outset, output signal waveforms and occurrence probabilities thereof at the first stage of the logic gates are calculated by the use of signal waveforms and occurrence probabilities thereof at primary input terminals of the integrated circuit; (2) next, output signal waveforms and occurrence probabilities thereof at the second stage of the logic gates are calculated by the use of the output signal waveform and the occurrence probability thereof at the primary input terminals and the output signal waveform and the occurrence probability thereof at the first stage of the logic gates; and (3) then, output signal waveforms and occurrence probabilities thereof at the n-th stage (n is a natural number) of the logic gates are calculated by the use of the output signal waveform and the occurrence probability thereof at the primary input terminals and the output signal waveform and the occurrence probability thereof at the (n-1)th stage of the logic gates. Thereby, types of the respective elementary waveforms, occurrence probabilities and signal correlations are calculated relating to signals located on each wiring of each stage inside of the integrated circuit and occurring within a predetermined time period.
REFERENCES:
patent: 5557531 (1996-09-01), Rostoker et al.
patent: 5682320 (1997-10-01), Khouja et al.
patent: 5847966 (1998-12-01), Uchino et al.
patent: 5872471 (1999-02-01), Ishibashi et al.
patent: 5966523 (1999-10-01), Uchino
patent: 6272663 (2001-08-01), Uchino
patent: 6324679 (2001-11-01), Raghunathan et al.
patent: 6363515 (2002-03-01), Rajgopal et al.
“Power Estimation Techniques for Integrated Circuits”, Najm, Proceedings International Conference on CAD, IEEE 1995.
Power Minimization in IC Design: Principles and Applications, Pedram, ACM Tranactions on Design Automation, vol. 1, No. Jan. 1996.
Najm et al.; “Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits”, IEEE Transactions on Computer-Aided Design, vol. 9, No. 4, pp. 439-450, (1990).
Tsui et al.; “Efficient Estimation of Dynamic Power Consumpton Under a Real Delay Model”, International Conference on Computer-Aided Design, pp. 224-228, (1993).
Uchino et al.; “Switching Activity Analysis using Boolean Approximation Method”, International Conference on Computer-Aided Design, pp. 20-25, (1995).
Copy of U.S. Appl. No. 09/312,828, Now US Patent No. 6,272,663.
Ferris Fred
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Teska Kevin J.
LandOfFree
Method for estimating power consumption and noise levels of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for estimating power consumption and noise levels of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for estimating power consumption and noise levels of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3608418