Method for ESD protection circuit with deep source diffusion

Details Method for ESD protection circuit with deep source diffusion Method for ESD protection circuit with deep source diffusion

1995-01-19

1997-07-08

Tsai, Jey

Fishing, trapping, and vermin destroying

437 40AS, 437 40GS, 437 41AS, 437162, 437904, H01L 2170, H01L 2700

Patent

active

056460627

ABSTRACT:
An improved semiconductor structure forms a series of FETs that are each connected between an input pad and ground for protecting the semiconductor device from an electrostatic discharge that may appear at the pad. Diffusions form alternate drain and source regions and are spaced apart at the surface of the device. Gate electrodes are located over the substrate between the diffusions so that the drain diffusion on one side of a gate also forms the drain for the FET on the one side and the source diffusion on the other side also forms the source diffusion for an FET on the other side. The electrical connection between the pad and the drain diffusions is formed by connections through the overlying insulation to a midpoint in the drain diffusion. Electrical connections between the gate and ground are formed by extending the conductive pattern that forms the gate. An electrical connection is made between the source diffusion and the gate electrode by a buried contact technique. A conductor is formed over the source diffusion as part of the process of forming the gate electrode, and the two electrodes are physically and conductively connected. The drain diffusions are made deeper than the source diffusions.

REFERENCES:
patent: 5060037 (1991-10-01), Rountree
patent: 5081514 (1992-01-01), Ueoka
patent: 5087955 (1992-02-01), Futami
patent: 5366908 (1994-11-01), Pelella
patent: 5372956 (1994-12-01), Baldi
patent: 5374565 (1994-12-01), Hsue et al.
patent: 5416036 (1995-05-01), Hsue

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