Method for erasing split-gate flash memory

Static information storage and retrieval – Floating gate – Particular biasing

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36518528, 36518514, 36518501, 36518515, G11C 1604

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active

059782749

ABSTRACT:
A method of erasing a split gate flash memory cell is provided, which can be used in the operation of a split gate flash memory cell to increase the number of its rewritable cycles. The improvement is remarkable especially for flash memory cells while its floating gate channel length is under a 0.4 .mu.m-feature size. The erasing method includes the steps of: (i) applying a negative voltage to the control gate and applying a positive voltage to the drain to form a forward electrical field between the drain and the control gate; and (ii) applying a positive voltage to the source to reduce a voltage difference between the drain and the source, so that electrons in the floating gate are discharged under the effect of the forward electrical field generated by the Fowler-Nordheim tunneling effect, and hot holes can be reduced and prevented from accumulating in a tunnel oxide between the floating gate and the drain, thereby erasing the split-gate flash memory cell, and increasing the number of rewritable cycles for the flash memory cell.

REFERENCES:
patent: 5212541 (1993-05-01), Bergemont
patent: 5280446 (1994-01-01), Ma et al.
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5801993 (1998-09-01), Choi
patent: 5847996 (1998-12-01), Guterman et al.
patent: 5856943 (1999-01-01), Teng

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