Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-09
2001-07-03
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290
Reexamination Certificate
active
06256228
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an erasing method of a floating gate type nonvolatile semiconductor storage device.
In recent years, there has been a demand for reducing the power consumption in accordance with increase of integration level in a flash memory of a nonvolatile semiconductor storage device. In response to the above demand, a reduction in consumption of power is enabled by using the Fowler-Nordheim tunneling phenomenon for write (program) and erase operations. The flash memory that executes the write and erase operations utilizing the Fowler-Nordheim (referred to as FN hereinafter) tunneling phenomenon is called the FN—FN type flash memory.
On the other hand, flash memories are classified by the memory cell array structure, and four principal types will be enumerated hereinbelow.
[1] The Institute of Electronics, Information and Communication Engineers Technical Report, ICD93-128, p37, 1993
An AND type flash memory reported as ““AND” cell structure for a 3V-only 64Mbit Flash Memory”
[2] The Institute of Electronics, Information and Communication Engineers Technical Report, ICD93-26, p15, 1993
A DINOR type flash memory reported as “A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory”
[3] IEDM Technical Digest, p263-266, 1995
A DuSNOR type flash memory reported as “A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories”
[4] IEDM Technical Digest, p267-270, 1995
An ACT type flash memory published in “A New Cell Structure for Sub-quarter Micron High Density Flash Memory” and “A sensing Scheme for a ACT flash memory” of The Institute of Electronics, Information and Communication Engineers Technical Report, ICD97-21, p37, 1997
The above types are published by several companies.
According to the flash memories of the above types [1] through [4], it is acceptable to execute electrical writing (program) and erasing on a memory cell. However, a voltage is applied to the drain, source or control gate of the selected memory cell in the write operation and the erase operation, while a voltage is also applied to the drain, source or control gate of the unselected memory cell. The threshold voltage of the unselected memory cell is changed by the influence of this voltage application, possibly causing erroneous reading
In recent years, there is an increasing trend toward using a method for applying a negative voltage to the semiconductor substrate (well) in order to reduce the absolute value of a voltage to be used inside the flash memory in the erase operation. This negative voltage applied to the semiconductor substrate brings the unselected memory cell whose drain, source or control gate receives the voltage into a lightly erased state, exerting bad influence (referred to as a substrate disturbance hereinafter) on the threshold voltage of the unselected memory cell. The substrate disturbance tends to become more severe as the flash memory comes to have a larger capacity.
The aforementioned substrate disturbance will be described by taking the ACT (Asymmetrical Contactless Transistor) type flash memory as an example.
FIG. 6
shows a sectional view of one memory cell of the above ACT type flash memory, and the principle of operation of the ACT type flash memory will be described with reference to FIG.
6
.
In the above ACT type flash memory of
FIG. 6
, a tunnel oxide film
14
, a floating gate
15
, an interlayer insulating film
16
and a control gate
17
are lamellarly formed on a substrate (p-type well)
11
so as to form a bridge between a drain
13
and a source
12
formed on the substrate
11
. Then, the drain
13
and the source
12
have different donor concentrations.
In the case of a program operation in the ACT type flash memory having the aforementioned construction, that is, in the case where electrons are extracted from the floating gate
15
to provide a written state (data “0”), a negative voltage Vnw (−8 V) is applied to the control gate
17
and a positive voltage Vpp (+5 V) is applied to the drain
13
, thereby extracting electrons from the floating gate
15
by the Fowler-Nordheim (referred to as FN hereinafter) tunneling phenomenon with the source
12
brought into the floating state. By this a program operation, the threshold voltage of the memory cell is lowered to a voltage of about 1.5 V.
In the case of an erase operation, that is, in the case where electrons are injected into the floating gate
15
to provide an erased state (data “1”), a positive voltage Vpe (+10 V) is applied to the control gate
17
, a negative voltage Vns (−8 V) is applied to the source
12
, and the drain
13
is brought into the floating state. Electrons are injected into the floating gate
15
by the FN tunneling phenomenon. Therefore, the threshold voltage of the memory cell is increased to a voltage of about 4 V or more.
In the case of a read operation, a voltage of +3 V is applied to the control gate
17
, a voltage of +1 V is applied to the drain
13
, and a voltage of 0 V is applied to the source
12
. The data is read by the sensing circuit (not shown) for sensing the current flowing through the memory cell.
The voltages applied to the memory cell in the program, aforementioned operations are shown in Table 1.
TABLE 1
Control
Substrate
Gate
Drain
Source
P-Type Well
Program
−8 V
5 V
Open
0 V
Operation
Erase
10 V
Open
−8 V
−8 V
Operation
Read
3 V
1 V
0 V
0 V
Operation
In order to explain the substrate disturbance in the erase operation, the application voltage in the erase operation will be described with reference to the array structure of the ACT type flash memory shown in FIG.
7
. As schematically shown in
FIG. 7
, the array structure of the ACT type flash memory has a virtual-ground-type array structure in which two memory cells jointly own an identical bit line.
In the above ACT type flash memory are shown main bit lines BL
0
through BL
4096
, sub-bit lines SBL
00
through SBL
04096
and SBL
10
through SBL
14096
formed from a diffusion layer (the sub-bit lines being in a layer different from that of the main bit lines), word lines WL
0
through WL
63
, selection gate signal lines SG
0
and SG
1
of selection transistors ST
00
through ST
04096
for selecting each block and a contact section CN (the portions each being indicated by the mark ▪ in
FIG. 7
) of the main bit lines BL
0
through BL
4096
and the sub-bit lines SBL
00
through SBL
04096
and SBL
10
through SBL
14096
. Then, in regard to the memory cells M
00
, M
01
, ... , M
10
, M
11
, ..., the number of contacts is reduced by making the memory cells of adjoining lines jointly own the sub-bit lines SBL
01
through SBL
04095
and SBL
11
through SBL
14095
and using the diffusion layer for the sub-bit lines SBL
00
through SBL
04096
and SBL
10
through SBL
14096
, by which the array area is sharply reduced, allowing high-density integration to be achieved.
FIG. 8
schematically shows the sub-bit lines SBL
00
through SBL
04096
and SBL
10
through SBL
14096
(shown in
FIG. 7
) formed from the aforementioned diffusion layer in the form of a cross-section of the essential part of the ACT type flash memory.
As shown in
FIG. 8
, an interlayer insulating film
22
, a floating gate
23
(FG) and a control gate
24
(WL) are lamellarly arranged on a semiconductor substrate
20
on which a sub-bit line
21
(diffusion layer) is formed. Then, the common sub-bit line
21
provided below the end portion of adjoining floating gates
23
(FG) has donor concentrations that differ between a drain
21
a
and a source
21
b.
In the case of the aforementioned ACT type flash memory, the erasing operation is executed on a block basis. In the erase operation, for example, a positive voltage (+10 V) is applied to the word lines WL
0
through WL
31
connected to the control gates of the memory cells M
00
, M
01
, . . . of a selected block BL
Morrison & Foerster / LLP
Phan Trong
Sharp Kabushiki Kaisha
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