Method for erasing nonvolatile memory cells in a field programma

Details Method for erasing nonvolatile memory cells in a field programma Method for erasing nonvolatile memory cells in a field programma

1999-05-14

2000-09-26

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 326 39, G11C 1600

Patent

active

061250597

ABSTRACT:
In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a buried N+ region for programming the cell, use a high voltage on the common control gate for the cell erasing operation. The source/drains of the switch transistor are grounded. By placing an intermediate voltage on the source/drains of the second transistor, erase times can be reduced and test costs can be significantly lowered.

REFERENCES:
patent: 5615150 (1997-03-01), Lin et al.
patent: 5914904 (1999-06-01), Sansbury
patent: 5969992 (1999-10-01), Mehta et al.
patent: 5999449 (1999-12-01), Mehta et al.

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