Method for erasing data in EEPROM devices on SOI substrates and

Details Method for erasing data in EEPROM devices on SOI substrates and Method for erasing data in EEPROM devices on SOI substrates and

1994-06-01

1995-10-03

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 257316, 257318, G11C 1700

Patent

active

054557917

ABSTRACT:
A simple stacked gate Electrically Erasable Programmable Read Only Memory (EEPROM) device fabricated on Silicon-on-Insulator (SOI) substrates(films) and a method to erase data in such device as well as in any other EEPROM devices fabricated on SOI substrates(films) is described. The new EEPROM device incorporates two separate control gates, a front control gate and a back control gate. In the new erasing method the back control gate is used to operate back channel of the EEPROM device in the avalanche region and generate hot carriers subsequently injected into the floating gate. The new erasing method is applicable to either n-channel or p-channel, inversion, accumulation or depletion mode devices.

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Sinha et al., "Generation and Annihilation of Interface States Under Alternate Hot Electro/Hole Injection in SOI MOSFETs", Oct. 3-6, 1994, IEEE International SOI Conference.
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