Static information storage and retrieval – Floating gate – Particular biasing
Patent
1994-06-01
1995-10-03
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
365218, 257316, 257318, G11C 1700
Patent
active
054557917
ABSTRACT:
A simple stacked gate Electrically Erasable Programmable Read Only Memory (EEPROM) device fabricated on Silicon-on-Insulator (SOI) substrates(films) and a method to erase data in such device as well as in any other EEPROM devices fabricated on SOI substrates(films) is described. The new EEPROM device incorporates two separate control gates, a front control gate and a back control gate. In the new erasing method the back control gate is used to operate back channel of the EEPROM device in the avalanche region and generate hot carriers subsequently injected into the floating gate. The new erasing method is applicable to either n-channel or p-channel, inversion, accumulation or depletion mode devices.
REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 4004159 (1977-01-01), Rai et al.
patent: 4099196 (1978-07-01), Simko
patent: 4162504 (1979-07-01), Hsu
patent: 4297719 (1981-10-01), Hsu
patent: 4412311 (1983-10-01), Miccoli et al.
patent: 4462089 (1984-07-01), Miida
patent: 4876582 (1989-10-01), Janning
patent: 4884239 (1989-11-01), Ono et al.
patent: 4888734 (1989-12-01), Lee et al.
patent: 5341342 (1994-08-01), Brahmbhatt
patent: 5350938 (1994-09-01), Matsukawa
Sinha et al., "Generation and Annihilation of Interface States Under Alternate Hot Electro/Hole Injection in SOI MOSFETs", Oct. 3-6, 1994, IEEE International SOI Conference.
Zaleski et al., "Design and Performance of a New Flash EEPROM o SOI(SIMOX) Substrates", Oct. 3-6, 1994, IEEE International SOI Conference.
Muller et al., "Device Electronics for Integrated Circuits", .COPYRGT.1986, pp. 383-388.
Schroder, "Advanced MOS devices", .COPYRGT.1987, pp. 221-222.
Zaleski et al., "Mechanisms of Hot-Carrier Induced Degradation of SOI (SIMOX) MOSFET's," Microelectronic Engineering 22 (1993) 403-406.
Zaleski et al., "Successive Charging/Discharging of Gate Oxides in SOI MOSFET's by Sequential Hot-Electron Stressing of Front/Back Channel", IEEE Electron Device Letters, vol. 14, No. 9, Sep. 1993.
Yoshikawa et al., "Comparison of Current Flash EePROM Erasing Methods: Stability and How to Control," 1992, IEDM Conference Proceedings, pp. 595-598.
Yamada et al., "A Self-Covergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", 1991, IEDM Conference Proceedings, pp. 307-310.
Ioannou Dimitris E.
Zaleski Andrzei
Mai Son
Nelms David C.
Singla Abanti B.
Singla Gora L.
LandOfFree
Method for erasing data in EEPROM devices on SOI substrates and does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for erasing data in EEPROM devices on SOI substrates and , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for erasing data in EEPROM devices on SOI substrates and will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1081801