Method for erasing and verifying nonvolatile semiconductor memor

Details Method for erasing and verifying nonvolatile semiconductor memor Method for erasing and verifying nonvolatile semiconductor memor

1995-04-11

1997-09-16

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518522, 3651853, G11C 1134

Patent

active

056687591

ABSTRACT:
In a nonvolatile semiconductor memory device including memory cells, a predetermined number of the memory cells are simultaneously erased. Only when at least one of the memory cells is overerased, i.e., is in a depletion state, a threshold voltage recovering operation is performed upon all of the memory cells, to relieve the overerased memory cell and suppress the deviation of threshold voltage.

REFERENCES:
patent: 5293560 (1994-03-01), Harari
patent: 5483485 (1996-01-01), Maruyama
Seki et al., "Non-Volatile And Fast Static Memories", IEEE International Solid-State Circuits Conference, pp. 60-61, Feb. 14, 1990.
Yamada et al., "A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash Eeprom", IEDM.
Oyama et al., "A Novel Erasing Technology For 3.3V Flash Memory With 64Mb Capacity And Beyond", IEDM Technical Digest, pp. 607-610, (1982).

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