Method for erasing a semiconductor magnetic memory...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185290, C365S185050, C365S185030, C365S173000, C365S171000

Reexamination Certificate

active

07995402

ABSTRACT:
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

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