Method for erasing a flash memory cell or an array of such...

Details Method for erasing a flash memory cell or an array of such... Method for erasing a flash memory cell or an array of such...

2011-07-05

2011-07-05

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185180, C365S185190, C365S185220

Reexamination Certificate

active

07974136

ABSTRACT:
A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

REFERENCES:
patent: 5455792 (1995-10-01), Yi
patent: 2005/0207199 (2005-09-01), Chen et al.
patent: 2005/0207225 (2005-09-01), Chen et al.

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