Method for ensuring cycle ordering requirements within a hierarc

Details Method for ensuring cycle ordering requirements within a hierarc Method for ensuring cycle ordering requirements within a hierarc

1995-12-13

1997-12-23

Ray, Gopal C.

395292, 395308, 395468, G06F 1300, G06F 1338

Patent

active

057014221

ABSTRACT:
A mechanism for ensuring coherency between a system memory and a cache memory within a processing system including a first split transaction bus, the system memory being connected to the first split transaction bus; a second split transaction bus; a bus agent including the cache memory connected to the second split transaction bus, and a bus interface unit connecting the first and second split transaction busses for transferring bus cycles between the first and second split-transaction busses. The mechanism records bus cycles, such as read cycles, write cycles and cache line invalidate cycles, directed from the first split transaction bus to the second split transaction bus into a transaction queue within the bus interface unit, and sequentially transfers these cycles to the second split transaction bus in the order in which these cycles are recorded into the queue. In another embodiment of the invention, implemented in a system which utilizes a write post negation procedure for to indicate write completion, only read and invalidate cycles received from the first split transaction bus are placed within an ordering queue, while write cycles received from the first split transaction bus are immediately passed through to the second split transaction bus. However, when an invalidate cycle has been recorded to the queue, all write cycles received from the first split transaction bus are held until the queued invalidate cycle has started on the second split transaction bus.

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