Method for encoding/decoding digital data transmitted...

Coded data generation or conversion – Digital code to digital code converters – To or from minimum d.c. level codes

Reexamination Certificate

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C341S059000, C341S095000, C709S231000, C370S535000

Reexamination Certificate

active

06642862

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention concerns a method for encoding/decoding digital data transmitted via serial links.
It particularly concerns an encoding/decoding method of the so-called 8B/10B type, the letter “B” being the abbreviation for “bit.”
It applies more particularly to serial links of the high speed short distance type.
The invention also concerns a device for implementing the method.
Within the context of the invention, the term “digital data” should be understood in its most general sense. It includes the concepts of messages, binary words, etc., and generally all sequences of binary elements or bits, the length of which is determined by the particular application envisaged.
2. Description of the Related Art
Transmissions of the aforementioned byte are specifically characterized by the fact that they are not associated with a clock, unlike, for example, parallel transmissions of digital data. In the latter case, all the bits that compose a binary word, for example, are transmitted simultaneously, through as many physical links. It follows that in the case of a serial link, it is necessary to adopt measures for retrieving clock information in the receiver.
Another constraint that must generally be obeyed is the need to guarantee a pre-established transition rate among all the bits constituting a binary sequence. Typically, it is desirable to obtain an average rate of 30% for a 1000-bit sequence.
Yet another constraint relates to the setting of a particular parameter known as “Maximum Run Length”(“MRL”), or the maximum number of successive bits that can remain at the same logical value, “0” or “1.”
In the prior art, in order to meet satisfy these requirements simultaneously, so-called “DC balanced” codes are most often used, i.e. codes that do not induce any DC component, at least within a pre-established time interval.
One of the characteristics of these codes is that they incorporate control and/or command words that specifically make it possible to retrieve clock signals on the receiving end of the binary sequences sent, but also control the sending and receiving procedures of the devices located at both ends of the chain (transmitter and receiver).
However, while this type of code makes it possible to solve, at least partially, the problems mentioned above, this technique is not without its drawbacks.
In particular, these codes involve the use of highly complex circuits. In practice, they are essentially used for “long distance” links.
One need that has arisen in recent information technologies is tied to the increase, in a single device or even in a single electronic circuit card, in the number of asynchronous serial links. For example, in a single device, there are card-to-card links. In a single card, there are links between modules or integrated circuits (“chips”). To illustrate the concept, the number of links can reach several tens of units, for example typically 72 asynchronous serial links between two “chips.”
SUMMARY OF THE INVENTION
In this context of the preferred application of the invention, the essential characteristic of the transmissions in question is that they take place over short distances—a few centimeters or even a few millimeters. Moreover, current technologies make it possible to use very high frequencies, commonly higher than 2.5 Mbps.
It is understood that, under these conditions, the solutions of the prior art, particularly the use of so-called “DC balanced” codes involving a high degree of complexity in terms of electronic circuits, cannot be satisfactory, especially since the proximity of the circuits and/or modules does not entail incorporating command words into the binary sequences transmitted.
FIG. 1
, attached to the present specification, schematically illustrates an exemplary architecture of asynchronous serial links,
11
and
12
, between two electronic circuit cards, C
1
and C
2
respectively, located in proximity to one another in a single unit
1
. A third electronic circuit card, which will be called a “management card” CM transmits control words MtC, for example via a single bus, to the two electronic circuit cards C
1
and C
2
, which are in close connection.
While it is not mandatory, for short distance links, to incorporate command words into the binary sequences transmitted, it is nonetheless necessary, no matter what encoding method is used, to meet all of the other requirements mentioned.
It is also important for the encoding process not to propagate the errors if one or more bits are set erroneously (inversion of their logical states). This requirement is particularly important when implementing means for detecting and correcting errors (codes known as “ERC” or “Error Recovery Codes”). Upon reception, the message decoded and processed by the “ERC” circuits should be identical to the original message sent, even if errors occur during transmission.
The object of the invention is to eliminate the drawbacks of the devices and systems of the prior art, some of which have been summarized, while meeting the needs that continue to arise.
In particular, the method according to the invention makes it possible to greatly simplify the encoding circuits required for its implementation, without deteriorating the quality of the transmissions.
More particularly, but not exclusively, the preferred applications of the invention concern an encoding of the so-called 8B/10B type. As indicated, the letter “B” stands for “bits.” This type of code is particularly advantageous because it makes it possible to handle bytes comprising exactly 8 bits, which will be qualified as data bits, since they convey information. The byte is completed by 2 additional bits, in specific logical states “1” or “0.” Such codes are intrinsically known. An example may be found in U.S. Pat. No. 5,025,256 A (International Computers Limited).
The main subject of the invention is a method for encoding/decoding digital data to be transmitted through a serial link, said digital data comprising a first so-called data bit sequence and a second so-called “label” bit sequence, characterized in that, said first and second sequences having first and second given bit lengths, it includes at least one encoding phase comprising at least a step for checking at least one slice of at least two consecutive bits, each of said slices being located in a predetermined area of said first bit sequence, so as to create a partitioning of the latter into parts of approximately equal length, said check consisting of performing a test to determine whether the consecutive bits of each of said slices are in the same logical state, “0” or “1,” a second step consisting of setting the bits of said second sequence to predetermined logical state configurations in one-to-one relation with the result of said test, and a step for inverting at least one bit of said slices when the result of said test is positive and for transmitting said first bit sequence without any modifications when the result of said test is negative.
Another subject of the invention is a device for implementing this method.


REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 5025256 (1991-06-01), Stevens
patent: 5229769 (1993-07-01), Gleichert
patent: 5699062 (1997-12-01), Widmer
patent: 5748119 (1998-05-01), Ko
patent: 5974464 (1999-10-01), Shin et al.
patent: 6111528 (2000-08-01), Bagley
patent: 6295010 (2001-09-01), Thiesfeld
patent: 6333704 (2001-12-01), Jung et al.
patent: 6346895 (2002-02-01), Lee et al.
patent: 6501396 (2002-12-01), Kryzak et al.
patent: 0 751 522 (1997-01-01), None
patent: WO 98 34413 (1998-08-01), None

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