Pulse or digital communications – Multilevel – Disparity reduction
Reexamination Certificate
1999-06-15
2002-11-05
Vo, Don N. (Department: 2631)
Pulse or digital communications
Multilevel
Disparity reduction
Reexamination Certificate
active
06477209
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to code conversion, and more particularly to conversion of recording codes which are used when digital data is recorded in a digital VTR, an optical disc storage, a magnetic disc storage and the like or which are used when digital data is transmitted via a transmission system.
BACKGROUND OF THE INVENTION
When digital data is recorded onto a recording medium in high density, or transmitted via any transmission system, (1, 7) code is conventionally used.
FIG. 11
shows an example of a conventional (1, 7) code conversion rule table.
This (1, 7) code conversion rule table includes 7 kinds of correspondence relations between data bits and channel bits, and shows that the following code conversion is performed. That is, data bits “00” are converted to channel bits “00X”, and, similarly, “01” are converted to “010”, “10” are converted to “10X”, “1100” are converted to “000010”, “1101” are converted to “00000X”, “1110” are converted to “100010”, and “1111” are converted to “10000X”. In this rule table, a symbol X designates an indefinite bit, and becomes “1” when the next channel bit following the indefinite bit is “0” and becomes “0” when the next channel bit following the indefinite bit is “1”. Also, recording or transmission of the (1, 7) code data is performed by using NRZI signal system. That is, the channel bits are sequentially disposed and “1” is converted to inversion of a signal and “0” is converted to non-inversion of the signal to record or transmit them.
The conventional (1, 7) recording code has the following characteristics. That is, at channel bit level, number of “0” existing between “1” and adjacent “1” is equal to or larger than 1 and equal to or smaller than 7. Therefore, when digital data is recorded and reproduced by using NRZI signal system, number of non-inversion bits existing between adjacent inversion bits can be equal to or larger than 1 bit and equal to or smaller than 7 bits. Thus, when a clock period of a signal after modulation or encoding is Ts, minimum interval between inversions becomes 2Ts and maximum interval between inversions becomes 8Ts. In practice, however, original bit number is multiplied by 1.5, because data bits having, for example, 2 bits are converted into channel bits having 3 bits. Therefore, with respect to a period Tb before modulation, timing relation becomes as follows.
Tmin=1.33Tb (minimum interval between inversions)
Tmax=5.33Tb (maximum interval between inversions)
Twin=0.67Tb (width of detection window)
The (1, 7) code has the characteristics mentioned above, and parameters Tmin, Twin, Tmin*Twin are relatively large so that a recording system using the (1, 7) code is suitable for high density recording. However, the conventional (1, 7) code has the following disadvantages.
In case code conversion is performed according to the (1, 7) code conversion rule table shown in
FIG. 11
, consider a condition in which data bits “10” and data bits “01” are alternately supplied. That is, data
“1001100110011001 . . . ”
is continuously inputted. In this case, channel bits become a repetition of “1” and “0”. That is, the channel bits become as follows.
“101010101010101010101010 . . . ”
This is a continuation of 2Ts patterns. Continuation of the 2Ts patterns is a pattern having maximum repetition frequency in the (1, 7) codes. If the 2Ts patterns continue in a data reproducing system, a signal level of a reproduced data reduces and a PLL (phase-locked loop) circuit used in the reproducing system tends to be out of synchronization. Therefore, it is necessary to avoid continuous occurrence of the 2Ts patterns for a long time as much as possible. However, in the conventional (1, 7) code, such continuous occurrence of the 2Ts patterns was inevitable.
In order to reduce bad influence of out of synchronization of the PLL circuit to minimum, conventionally, there is known a technique of periodically inserting a re-synchronizing signals into a recording data. For example, see Japanese patent laid-open publication No. 6-195893. However, since this technique is not a technique for avoiding occurrence of 2Ts patterns continuously for a long time, there was a problem that, depending on the locations of insertion of the re-synchronizing signals, the 2Ts patterns were produced continuously for a long time, thereby causing out of synchronization of the PLL circuit.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to obviate disadvantages of the conventional recording codes.
It is another object of the present invention to avoid continuous and long time occurrence of 2Ts patterns in recording codes.
It is still another object of the present invention to realize stable operation of a PLL circuit when reproducing digital data recorded onto a recording medium or transmitted via a transmission system.
It is still another object of the present invention to effectively decrease DC component of recording codes and to reduce bad influence caused by signal jittering.
It is still another object of the present invention to improve reliability of digital data storage or digital data transmission.
According to an aspect of the present invention, there is provided a method for encoding recording codes wherein data bits are encoded into channel bits. The method comprises: allotting respective channel bits “00X”, “010” and “10X” to 3 patterns of data bits among 4 patterns of data bits having 2 bits, where X designates an indefinite bit which becomes “1” when the channel bit succeeding the indefinite bit is “0” and becomes “0” when the channel bit succeeding the indefinite bit is “1” ; allotting channel bits “000010”, “00000X”, “100010” and “10000X” to 4 patterns of data bits having 4 bits which are a combination of two bits having a remaining one pattern among the 4 pattern of the data bits having 2 bits and additional two bits; and allotting channel bits “100000010” as a special pattern to data bits having 6 bits which are the continuation of alternate 3 patterns of data bits to be encoded to channel bits “010” and data bits to be encoded to channel bits “10X”.
According to another aspect of the present invention, there is provided a method for decoding channel bits encoded by the method mentioned above. In this method, from channel bits to be decoded having 3 bits, channel bits having 6 bits preceding the channel bits to be decoded and channel bits having 5 bits succeeding the channel bits to be decoded, decoded data bits having 2 bits are obtained.
According to still another aspect of the present invention, there is provided a method for encoding recording codes wherein data bits are encoded into channel bits. This method comprises: allotting respective channel bits “00X”, “010” and “10X” to 3 patterns of data bits among 4 pattern of data bits having 2 bits, where X designates an indefinite bit which becomes “1” when the channel bit succeeding the indefinite bit is “0” and becomes “0” when the channel bit succeeding the indefinite bit is “1”; allotting channel bits “000010”, “00000X”, “100010” and “10000X” to 4 pattern of data bits having 4 bits which are a combination of two bits having a remaining one pattern among said 4 pattern of the data bits having 2 bits and additional two bits; and allotting channel bits “000000010” or “100000010” as a special pattern to data bits having 6 bits which are the continuation of alternate 3 patterns of data bits to be encoded to channel bits “010” and data bits to be encoded to channel bits “10X”, one of the channel bits “000000010” and “100000010” being selected according to a predetermined criterion. By this method, DC component of the recording codes can be further decreased and bad influence by signal jittering can be reduced.
According to still another aspect of the present invention, when, for example, DC component of an encoded digital signal is to be removed, it is possible to select one pattern of channel bits, such that DSV (Digital Sum Value) of an encoded data is minimized, among a plurality patterns of channel
Hayes & Soloway PC
Vo Don N.
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